10.2 Logic Gates – Pulse and Digital Circuits

10.2 LOGIC GATES

A logic gate is a circuit that gives either ‘0’ (LOW) level or ‘1’ (HIGH) level at the output, depending on the input conditions. The basic logic gates can be wired using discrete components such as resistors, diodes, transistors and FETs. The wiring of a complex gate circuit is unthinkable using discrete components. When the complexity of the gate circuit increases, it is preferable to wire the logic gate in an integrated circuit form. In this section, we basically describe the different types of logic gates using discrete components only, in order to understand the principle of operation of logic circuits of different logic families.

10.2.1 Simple Diode Gates

AND and OR are the two basic gates from which NAND and NOR gates can be derived. Here, we describe two types of diode gates—diode AND gates and diode OR gates.

Diode AND Gates. An AND gate is a digital circuit which gives a high output only when all the inputs are simultaneously high (1), otherwise the output is low (0). Consider a simple two-input AND gate using diodes (See Fig. 10.1).

Assuming D1 and D2 to be ideal diodes, the following cases are possible:

  1. Both the inputs are zero, the diodes are ON and Vo = 0.
  2. V1 = 0, V2 = 1, D1 is ON, D2 is OFF, Vo = 0.
  3. V1 = 1, V2 = 0, D1 is OFF, D2 is ON, Vo = 0.
  4. V1 = 1, V2 = 1, D1 and D2 are OFF, Vo = 1.

The truth table for the gate is given in Table 10.1. The schematic representation of the AND gate is shown in Fig 10.2(a).

The timing diagram for the two-input AND gate is shown in Fig 10.2(b). As mentioned in the preceding section, in an AND gate, the output is 1 only when all the inputs are 1 and, 0 if any one of the inputs is 0. Hence, in Fig. 10.2(b), at the instant T0, when both the inputs V1 and V2 are 0, the output Vo = 0. At T1, V1 = 0 and V2 = 1. Since one of the inputs is zero, the output Vo = 0. At the instant T3, V1 = 1 and V2 = 1. Since both the inputs are 1, the output Vo = 1 and so on. In general, there can be a large number of inputs to a gate. A NOT gate, also called an inverter in digital circuits, is schematically represented as in Fig. 10.2(c). Figure 10.2(d) shows the timing diagram for a NOT gate.

 

TABLE 10.1 The truth table for the AND gate

V1 V2 Vo
0 0 0
0 1 0
1 0 0
1 1 1

FIGURE 10.1 A two-input AND gate

FIGURE 10.2(a) The schematic diagram for the two-input AND gate

FIGURE 10.2(b) The timing diagram for two-input AND gate

FIGURE 10.2(c) A NOT gate

FIGURE 10.2(d) The timing diagram for a NOT gate

FIGURE 10.3(a) A NAND gate

In a NOT gate, the output is the complement of the input. This means, that if the input is 1, the output is 0; and if the input is 0, the output is 1. At To, the input V1 = 1; therefore, the output Vo = 0. At T1, the input V1 = 0 and output Vo = 1 and so on.

An AND gate cascaded with a NOT gate is called a NAND gate. Figures 10.3(a) and (b) show the schematic representation and the timing diagram of a NAND gate, respectively.

In a NAND gate, the output is 0 only when all the inputs are 1. If any one of the inputs is 0, the output is 1. As shown in Fig. 10.3(b), at the instant T0, both the inputs V1 and V2 are 0 and therefore, the output Vo is 1. At T1, V1 = 0 and V2 = 1. Since one of the inputs is 0, the output Vo is 1. At T3 both the inputs V1 and V2 are equal to 1 and therefore the output Vo = 0.

Diode OR Gates. An OR gate is a digital circuit which gives a high output when either one or all the inputs are high (1). In other words, the output is low (0) only when both the inputs are low. A two-input diode OR gate is shown in Fig. 10.4. Here too, we assume the diodes to be ideal. The following cases are possible:

FIGURE 10.3(b) The timing diagram for a NAND gate

  1. V1 = V2 = 0, D1 and D2 are OFF, Vo = 0
  2. V1 = 0, V2 = 1, D1 is OFF, D2 is ON, Vo = 1
  3. V1 = 1, V2 = 0, D1 is ON, D2 is OFF, Vo = 1
  4. V1 = 1, V2 = 1, D1 and D2 are ON and Vo = 1

The truth table for an OR gate is shown in Table 10.2. An OR gate is schematically represented as in Fig. 10.5(a).

FIGURE 10.4 The two-input diode OR gate

The timing diagram for a two-input OR gate is shown in Fig. 10.5(b). In an OR gate, when any one of the inputs is 1, the output is 1. It is 0 only if all the inputs are 0. Hence, in Fig. 10.5(b), at the instant T0, both the inputs V1 and V2 are 0; therefore, the output Vo is 0. At T1, V1 is 0 whereas V2 = 1. Since one of the inputs is 1, the output Vo = 1. At the instant T3, V1 is 1 and V2 is 1. Since both the inputs are 1, the output Vo = 1. An OR gate cascaded with a NOT gate is called a NOR gate, as represented in Fig. 10.6(a). Its timing diagram is shown in Fig. 10.6(b).

The output of a NOR gate is 1 when all the inputs are 0. When any one of the inputs is 1, the output is 0. Therefore, in Fig. 10.5(b), at the instant T0, when both the inputs V1 and V2 are 0, the output of the NOR gate is Vo = 1. At T1, V1 = 0 and V2 = 1; since one of the inputs is 1, the output Vo is 0. At T3, both the inputs V1 and V2 are equal to 1; therefore, the output Vo is 0.

 

TABLE 10.2 The truth table for an OR gate

V1 V2 Vo
0 0 0
0 1 1
1 0 1
1 1 1

FIGURE 10.5(a) An OR gate

FIGURE 10.5(b) The timing diagram for a two-input OR gate

FIGURE 10.6(a) A NOR gate

FIGURE 10.6(b) The timing diagram for a NOR gate

EXAMPLE

Example 10.1: The three-input AND gate shown in Fig. 10.7(a) is driven by the outputs of a bistable multivibrator. Transistors are capable of taking an additional current of 1 mA when in saturation. Fix the value of R1 and find the output for different input conditions.

FIGURE 10.7(a) The given three -input AND gate

Solution:

When Q1 is in saturation, Q2 and Q3 are OFF as shown in Fig. 10.14(b).

 

VCC = IR1R1 + VF + VCE(sat)

Therefore,

FIGURE 10.7(b) The circuit of Fig. 10.7(a) when Q1 is ON, Q2 and Q3 are OFF

This is the value of R1 to limit the additional current to 1 mA.

Vo(low) = VCE(sat) + VF = 0.2 + 0.6 = 0.8 V

When all the inputs to the AND are 1, diodes are OFF;

 

Vo(high) = VCC = 5 V

EXAMPLE

Example 10.2: For the three-input OR gate shown in Fig. 10.8(a), the supply voltage is 15 V. The inputs to the gate are supplied by bistable multivibrators. The output voltage is required to be 12 V for the logic level 1. Given VF = 0.6 V. Fix the value of R1.

FIGURE 10.8(a) The three-input OR gate

Let the inputs be 1, 0 and 0 for D1, D2 and D3, respectively. This means Q1 is OFF and Q2 and Q3 are ON. Then D1 is ON and D2 and D3 are OFF, as shown in Fig. 10.8(b).

 

VCC = I1RC + VF + Vo     I1RC = VCCVFVo

FIGURE 10.8(b) The circuit of Fig. 10.8(a) when Q1 is OFF Q2 and Q3 are ON

V0 for 1 level required to be 12V.

Therefore,

Therefore

10.2.2 Resistor–Transistor Logic Gates

An RTL gate uses the resistances and transistors for its operation. Figure 10.9 shows a resistor–transistor logic (RTL) NOR gate. If both the inputs V1 and V2 are 0, Q1 and Q2 are OFF and Vo = VCC (1 level). If any or both the inputs are 1, Vo = VCE(sat) (0 level). Hence, this is a NOR gate.

FIGURE 10.9 An RTL NOR Gate

EXAMPLE

Example 10.3: Verify that the alternate form of RTL gate in Fig. 10.10(a) is a NOR gate.

FIGURE 10.10(a) An RTL NOR gate

Solution:

(i) If both the inputs are 0 V, the resultant circuit is shown in Fig. 10.10(b).

As this voltage at the base of Q reverse-biases the emitter diode, Q is OFF:

 

Vo = 15 V(1 level).

If both the inputs are at 1 level (15 V), as shown in fig. 10.10(c)

FIGURE 10.10(b) The resultant circuit of Fig. 10.10(a) when both the inputs are 0

Hence, Q is in saturation.

Vo = 0 V(0 level)

If any one input is 1 (say 1) and the other input is 0 (say 2), the resultant circuit is shown in Fig. 10.10(d).

Thevenizing,

This voltage at the base of Q, drives the transistor into saturation. Thus, if any or both the inputs are 1, Vo = 0 level; with both the inputs 0, Vo = 1 level. Hence, the truth table is as shown in Table 10.3. Therefore, the RTL gate is a NOR gate.

FIGURE 10.10(c) The resultant circuit of Fig. 10.10(a) when both the inputs are 1

FIGURE 10.10(d) The resultant circuit of Fig. 10.10(a) when input 1 is 1 and input 2 is 0

 

TABLE 10.3 The truth table for a NOR gate

1 2 V0
0 0 1
0 1 0
1 0 0
1 1 0

10.2.3 Diode–Transistor Logic Gates

In the diode–transistor logic family (DTL), diodes and transistors are used as the basic building blocks. In this family, we consider the two basic gates—NAND and NOR.

DTL NAND Gates. A diode AND gate followed by a transistor inverter is a DTL NAND gate, as shown in Fig. 10.11 Here, we assume that the input at 1 is grounded. Diode D1 conducts. Then the voltage at A, VA = VF, the diode forward voltage. With this voltage (approximately equal to 0.7 V), diodes D3 and D4 will not conduct as they require a minimum voltage of 1.4 V to conduct. Hence, Q is OFF. Thus, if any one of the inputs to the NAND gate is zero, Q is OFF and Vo = VCC (1 level).

If, on the other hand, both the inputs are 1, then diodes D1 and D2 are reverse-biased and behave as open circuits. Diodes D3 and D4 then conduct and the voltage at the base of Q can drive it into saturation. Therefore, the output Vo = VCE(sat) (0 level). This gate produces a 0 output level when all the inputs are 1 and the 1 level at the output if any of the inputs is 0 (NAND gate). D3 and D4 are provided to derive noise immunity. In the NAND gate shown in Fig. 10.11, when D3 is replaced by a Zener diode (anode and cathode reversed) with a break-down voltage of 3.8 V, this gate gives an even better noise immunity. However, this requires high supply voltages. Such a gate is called a high-threshold logic (HTL) NAND gate. HTL is also sometimes referred to as HNIL (high noise immunity logic).

FIGURE 10.11 A DTL NAND gate

EXAMPLE

Example 10.4: Verify that the alternate form of the DTL circuit shown in Fig. 10.12(a) is a NAND gate. What is the minimum value of hFE to keep Q in saturation?

Solution:

FIGURE 10.12(a) A DTL NAND gate

FIGURE 10.12(b) The resultant circuit of Fig. 10.12(a) when the input 1 is 0 and the other is 1

FIGURE 10.12(c) The resultant circuit of Fig. 10.12(a) when both the inputs are 1

To verify that the circuit shown in Fig. 10.12(a) is a NAND gate, let us assume that input1 is 0 V and input 2 is at level 1, i.e., 15 V. Then D1 conducts as the voltage at the anode of D2 is VF (≈ 0 V) and that at the cathode is 15 V, D2 is OFF and is open circuited. The voltage at P is 0 V, as shown in Fig. 10.12(b).

TABLE 10.4 The truth table for a NAND gate

1 2 V0
0 0 1
0 1 1
1 0 1
1 1 0

As VB reverse-biases the emitter diode, Q is OFF and Vo = 15 V (1 level). If all the inputs are 15 V (1 level), both the diodes are OFF.

Hence, Q is in saturation. Consequently, Vo = 0 V (0 level). The truth table for this is shown in Table 10.4. Hence, the circuit is a NAND gate.

(ii) Calculating the minimum value of hFE to keep Q in saturation

Consider the equivalent circuit of Fig. 10.12(a). When Q is in saturation, VCE(sat) = 0, VBE(sat) = 0 when compared to the supply voltages of 15 V, as shown in Fig. 10.12(d).

 

I1 = I2 + IB    IB = I1I2

FIGURE 10.12(d) The resultant circuit of Fig. 10.12(a) when Q is in saturation

And

FIGURE 10.13 A DTL NOR gate

FIGURE 10.14 A transistor inverter with an output low

DTL NOR Gates. A DTL NOR gate comprises a diode OR gate followed by a transistor inverter, as shown in Fig. 10.13. When both the inputs V1 and V2 are 0, Q1 is OFF and Vo = VCC(1 level). If any input, say V1 is 1, D1 is ON and the voltage at the base of Q1 is 5 V. Consequently, Q1 is in saturation and Vo = VCE(sat) (0 level).