10.3 FACTORS DEFINING THE PERFORMANCE OF LOGIC GATES
The following factors define the performance of a logic gate:
Supply voltage: TTL IC logic gates are normally designed to operate with a supply voltage of 5 V whereas CMOS gates can operate in the range of 1–30 V. When a supply voltage of 5 V is specified for a gate, it is expected that the voltage variation remains within ±0.25 V of 5 V for reliable gate operation.
Input voltages and currents: For a gate to operate properly, it should have minimum high-input voltage, VIH(min), which represents the logic 1 input level.
As an example, let VIH(min) = 2 V for a gate. It means that the output of the gate changes only when the input is greater than or equal to 2 V. Consider the transistor inverter shown in Fig. 10.14.
Let Q1 be OFF in which case the voltage at its collector is VCC(1 level). To switch this output to a 0 level, the minimum high-input voltage is given as:
VIH(min) = IIH(min)RB + Vσ
where, IIH is the high-level input current sufficient enough to drive the transistor into saturation.(Typically, this value is 1 mA.)
Similarly, each type of gate has a maximum low-input voltage, VIL(max), which is the highest voltage acceptable as the logic 0 input. Consider the circuit shown in Fig. 10.15. VIL(max), therefore, must be much smaller than Vγ. For silicon transistors, VIL(max) is typically 0.2 V. Any voltage above this level will not be accepted as a low-level input by the logic circuit. IIL(max) is the current that flows into an input when VIL(max) is applied at the input. The low-level input current IIL occurs when Q2 is OFF. In actuality, the junction leakage current is less than 1 μA
Output currents and voltages: The output current from a gate is termed as a high-level output current, IOH, when the gate output voltage, VOH, is high. Consider the circuit shown in Fig. 10.16.
FIGURE 10.15 A transistor inverter with a high output
FIGURE 10.16 The output voltage and current when the gate output is high
Here, the device Q is OFF and IOH(max) is the maximum high-level output current through the load. IOH(max) is a positive quantity and the current flows out of the gate terminal. The gate is now said to source the output current and is called a current source. The minimum output voltage for a logic 1 level is called VOH(min)., given by the relation:
VOH(min) = VCC − IOH(max)RC.
Sometimes the output of a gate is required to drive the inputs of several gates. This requirement stipulates that the minimum logic 1 output voltage of a driving gate should be greater than or equal to the minimum logic 1 input of the driven gates, that is, VOH(min) ≥ VIH(min). The output current when the gate output voltage is low is called the low-level output current IOL and the corresponding voltage VOL is the low-level output voltage.
Consider the output of the gate shown in Fig. 10.17. Here, the low-level output current, IOL, is generally a negative quantity. In other words, the current flows into the output terminal. The gate is now said to sink this current and the output is called a current sink. For the circuit shown in Fig. 10.17, VOL(max) = VCE(sat) = 0.2 V. If this gate is required to drive the input of several gates, VOL(max) has to be lower than VIL(max)
Fan-out: The output of a logic gate may have to drive inputs of several similar logic gates. The maximum number of inputs (to several gates) that the output of any one gate can drive is called fan-out or loading factor of the gate. For example, if the fan-out of a logic gate is specified as five, it means that the gate can drive five inputs from the same family.
FIGURE 10.17 The output voltage and current when the gate output is low
The fan-out, when the output of a gate is at logic level 1, is indicated in Fig. 10.18(a).
FIGURE 10.18(a) The fan-out when the output of a gate is at logic level 1
FIGURE 10.18(b) The fan-out when the output of a gate is at 0 level
The fan-out when the output of a gate is high is:
For standard TTL, IOH(max) = 400 μA and IIH(max) = 40 μA
This means, that the standard TTL gate can drive the inputs of 10 other identical gates. The fan-out, when the output of a gate is at 0 level, is shown in Fig. 10.18(b).
The fan-out when the output of a gate is low,
For standard TTL, where IOL(max) = 16 mA and IIL(max) = 1.6 mA are typical currents.
The fan-out in both the cases is 10. However, in practice, it is the smaller value, that is taken into account.
Fan-in: Fan-in normally refers to the number of inputs of a gate. A gate can have one input as in an inverter. In this case the fan-in is 1. An OR gate may have two inputs. Then, the fan-in is 2 and another AND gate may have four inputs for which the fan-in is 4. In general, the smaller is the fan-in the faster is the gate.
Propagation delay: In logic gates, diodes and transistors are used as switches. Proper fabrication techniques can help reduce the influence of stray capacitances to a minimum. However, it is practically impossible to eliminate the influence of these stray capacitances. These stray capacitances influence the switching speed of a device, as a consequence of which the output does not respond to an input instantaneously and may have a rise time though the input to the gate is a pulse with zero rise time. If the output of the first gate is the input to another gate, there is further distortion in the amplitude of the signal and this effect becomes cumulative when the signal passes through several gates. Thus, when the signal passes thorough several gate combinations, it is subjected to time delay and (possibly) appreciable distortion, which limits the utility of the gate. Hence, while using a gate for a specific application, we need to know the propagation delay. The time interval from the instant the input pulse is applied to the gate to the time of occurrence of the resultant output pulse is called the propagation delay of the gate. Propagation delay specifies the switching speed of the gate. Alternatively, propagation delay can also be defined as the time required for the gate to switch from a low-output state to a high-output state and vice versa. Consider the gate shown in Fig. 10.19(a).
The following method is used for measuring the propagation delay. Consider a simple inverter gate with a finite propagation delay, where the output is shifted in the phase by 180°, as shown in Fig. 10.19(b).
On the other hand, if the output of the gate is in the same phase as the input with only a propagation delay as shown in Fig. 10.19(c):
FIGURE 10.19(a) A basic gate
tPLH = Time for the output to go from low to high
tPHL = Time for the output to go from high to low.
These times are measured between the 50 per cent levels of the input and output. Normally, tPLH ≠ tPHL. In some cases, propagation delay, tP is taken to be the larger of these two values, i.e., propagation delay, tP = max(tPLH, tPHL). More realistically, it is taken as the average of these two values i.e.,
Noise immunity: In a logic gate, both the input and the output are either 0 level or 1 level, representative of dc voltages or pulse amplitudes. We already know that each gate has a maximum low-input voltage, VIL(max), which is the highest voltage acceptable as a 0 input and a minimum high-input voltage, VIH(min), acceptable as a 1 level at the input. Noise (unwanted signals at the input) sometimes may change the voltage at the input of a gate that may lead to unpredictable operation of a gate.
Noise immunity is the ability of the logic gates to tolerate changes at the input due to noise but still deliver the predictable output. Consider the input and output voltage levels of a logic gate as shown in Fig. 10.20.
Low-state noise margin, VNL = VIL(max) − VOL(max)
High-state noise margin, VNH = VIH(min) − VOH(min)
FIGURE 10.19(b) The inverter propagation delay
FIGURE 10.19(c) The non-inverter propagation delay
FIGURE 10.20 The input and output voltage levels of a logic gate and its noise immunity
Noise spikes greater than the noise margins specified may drive the gate into an intermediate range. This gives rise to ambiguity. Data sheets normally specify noise immunity for a gate as poor, fair, good or excellent.
Power dissipation: When batteries supply power to logic gates, the drain on the battery should be minimum. For this to happen we must use gates with the lowest dissipation possible. Typically power dissipation varies from 10 nW to 25 μW per gate, depending on the circuitry. Power dissipation is generally large in a gate that switches fast (TTL gate) because, for faster switching, the transistor is held in the active region. Generally, a circuit employing many gates may generate more heat. Obviously, in such cases, the gates that have the least power dissipation are desirable. Hence, in applications where power dissipation is the major consideration in the choice of a gate, CMOS gates are preferred over TTL gates.
Figure of merit: The figure of merit of a logic gate is the product of propagation delay and the average power dissipation. The smaller the figure of merit the better is the performance of the gate. The figure of merit is also called the speed-power product.
Figure of merit = Propagation delay (seconds)× average power dissipation (Watts) = Joules/s
FIGURE 10.21(a) The positive logic
FIGURE 10.21(b) The negative logic