10.4 Positive Logic, Negative Logic and Logic Circuit Conversion – Pulse and Digital Circuits

10.4 POSITIVE LOGIC, NEGATIVE LOGIC AND LOGIC CIRCUIT CONVERSION

Positive logic: If the signal that activates the logic gate has for its high (1) level a voltage more positive than for its low (0) level then the polarity of the logic is called positive logic, as shown in Fig. 10.21(a).

Negative logic: If the signal that activates the logic gate has for its high (1) level a voltage more negative than for its low (0) level then the polarity of the logic is called negative logic, as shown in Fig. 10.21(b).

Logic circuit conversion: A circuit using a positive (negative) logic can be converted into a circuit performing the same logic function but with a negative (positive) logic by following the procedure listed below.

Step 1. Reverse the polarities of all supply voltages.

Step 2. Reverse the polarity of the driving signals (input voltages).

Step 3. The polarities of all diodes are reversed and all transistors are changed from p–n–p to n–p–n and vice versa. Consider Example 10.5 to verify this procedure.

EXAMPLE

Example 10.5: Consider the NOR gate with a positive logic shown in Fig. 10.21(c). In the positive logic a ‘0’ level is 0 V and ‘1’ level is V. In this example V = 10 V. Obtain the truth table for a positive logic and verify with the negative logic.

FIGURE 10.21(c) The DTL NOR gate with a positive logic

Solution:

For the circuit shown in Fig. 10.21(c), if both the inputs are of 0 V, diodes D1 and D2 conduct. Then, the voltage at P is 0 V. The voltage at the base of Q, VB, is calculated using the circuit shown in Fig. 10.21(d).

Hence, Q is OFF. Therefore, Vo = 10 V (1 level).

If the input 1 is 10 V and the input 2 is 0 V, then D1 is ON and the voltage at P is 10 V. This reverse-biases the diode D2 and it is OFF. The corresponding circuit is shown in Fig. 10.21(e).

The voltage at the base of Q, VB now is:

Hence, Q is in saturation and Vo≅0 V. The conditions are tabulated in the truth table given in Table 10.5. Hence, the circuit is a positive NOR.

To convert the positive NOR into a negative NOR, follow the given steps:

  1. Let the driving input now have 1 level as −10 V and 0 level as 0 V (negative logic).
  2. Reverse the polarity of the supply voltages.
  3. Reverse the polarities of the diodes.
  4. Replace the n-p-n transistor by a p-n-p transistor. Then, the circuit is still a NOR gate, but now with a negative logic, as shown in Fig. 10.21(f).

When both the inputs are −10 V (1 level), VB = −8.18 V, Q is ON and Vo = 0 V (0 level). When both the inputs are at 0 level (0 V), VB = 0.91 V, Q is OFF and Vo = −10 V (1 level). Thus, this circuit is also a NOR gate but with a negative logic.

Let us consider a logic gate and let a voltage V1 be added to all the supply voltages, to all leads that are grounded and to both the binary levels (0 and 1). Then it can be verified that the logic function performed by the circuit to which these voltages are added is again the same as that of the original circuit.

FIGURE 10.21(d) The circuit to calculate the output, when both the inputs are ‘0’

FIGURE 10.21(e) The circuit to calculate VB, when input 1 is 10 V and input 2 is 0 V

 

TABLE 10.5 The truth table for a positive logic

V1 V2 V0
0 0 1
0 1 0
1 0 0
1 1 0

FIGURE 10.21(f) The DTL NOR gate with a negative logic (1 level is −10 V and 0 level is 0 V)

FIGURE 10.21(g) The equivalent circuit of 10.21(f) when V1 = 2 V is added

To illustrate this consider the circuit shown in Fig. 10.21(f). If V1 = 2 V is added, then the circuit is redrawn as shown in Fig. 10.21(g). This circuit performs the same logic operation as the circuit shown in Fig. 10.21(f).

10.4.1 Transistor–Transistor Logic Gates

In transistor–transistor logic (TTL) gates, the inputs are directly connected to the input terminals of the transistors. In this logic family, bipolar junction transistors are used as the basic building blocks. Let us consider two types of TTL gates, a TTL NAND gate and a TTL NOR gate.

TTL NAND Gates. Fristly consider the basic TTL NOT gate, shown in Fig. 10.22(a). When the input to the gate Vi = 0 (i.e., emitter is grounded), the base–emitter diode of Q1 is forward-biased by a large voltage which drives the transistor into saturation. Therefore, the voltage between the collector and emitter (grounded) terminals is VCE(sat) which is typically 0.2 V and cannot drive Q2 ON. Hence, Q2 is OFF and its output is Vo = VCC(1 level). Thus, when the input is 0, the output is 1 as shown in Fig. 10.22(b).

FIGURE 10.22(a) A TTL NOT gate

FIGURE 10.22(b) The circuit of Fig. 10.22(a) when the input is low

FIGURE 10.22(c) The circuit of Fig. 10.22(a) when the input is high

FIGURE 10.22(d) A multi-emitter transistor

Now, if a high input is applied (Vi = 5 V), the base–emitter diode of Q1 is reverse- biased. As Q1 cannot go into the OFF state immediately, VCE(sat) still exists between the collector and emitter terminals of Q1. Hence, the net voltage at the collector of Q1 is Vi + VCE(sat). This voltage at the base of Q2 drives it into saturation. As a result, its output Vo = VCE(sat) = 0.2 V (0 level), as shown in Fig. 10.22(c). Thus, if the input is 1, the output is 0 and vice versa. Hence, this is a TTL NOT gate.

To ensure that more number of inputs can be connected to the gate, Q1 can be a transistor with more number of emitters. A three-emitter transistor is shown in Fig. 10.22(d).

A two-input TTL NAND gate is shown in Fig. 10.22(e). When all the inputs are at 1 level, Q2 is ON and in saturation. Therefore, the output Vo is a 0 level. When any or both the inputs are at 0 level (grounded), Q2 is OFF and the output Vo is at 1 level. Hence, it is a NAND gate. Standard TTL gates are usually referred to as 74 or 7400 series and 54 or 5400 series. A 54 series gate operates over a wider temperature range (-55°C to +125°C) and can tolerate variations of the supply voltage by ±0.5 V (i.e., the supply voltage variation can be from 4.5 V to 5.5 V). A 74 series operates in the temperature range of 0 to 70°C and the supply voltage variation can only be ±0.25 V (i.e., the supply voltage can vary from 4.75 V to 5.25 V). A two-input 74 series TTL NAND gate is shown in Fig. 10.22(f).

Diodes D1 and D2 are included in the gate circuit shown in Fig. 10.22(f). If, for any reason, the input has negative spikes, then diodes D1 and D2 conduct to limit the amplitude of these spikes. Apart from this, these diodes have no other specific role in the operation of the gate. To understand the operation of the gate, for all practical purposes diodes D1 and D2 can be disconnected. The gate circuit thus obtained is shown in Fig. 10.22(g).

When both the inputs are at 1, Q1 is OFF and the voltage at the base of Q2 is large. As such, Q2 goes ON and into saturation. Hence, Q3 is OFF and Q4 is ON (saturation). As a result, the output Vo is pulled down and is at 0 level. With these inputs, drawing the output circuit only results in the circuit shown in Fig. 10.22(h).

FIGURE 10.22(e) The two-input TTL NAND gate

FIGURE 10.22(f) A 74 series two-input TTL NAND gate

FIGURE 10.22(g) The practical TTL NAND gate

FIGURE 10.22(h) The circuit when both the inputs are at1(Q3 is OFF and Q4 is ON)

FIGURE 10.22(i) The circuit when any one input is at 0 (Q3 is ON and Q4 is OFF)

If any one of the inputs is at 0, Q1 is in saturation and the voltage at the base of Q2 is VCE(sat), which is small. Therefore, Q2 is OFF. Hence, Q3 is ON and Q4 is OFF. The output circuit is drawn as shown in Fig. 10.22(i).

The output is now at 1 level. Q3 provides an active pull-up, that is, the output now at 1 level.

We have seen that when both the inputs are high (1level = 5 V), the base–emitter junctions of Q1 are reverse-biased and Q1 is OFF. Hence, the voltage at the base of Q2 is large. As a result, Q2 is driven into saturation and consequently, Q4 goes into saturation. Therefore, Vo = 0.2 V (0 level). Now if suddenly, one of the inputs goes low, the output is expected to jump to 1 level abruptly. This is possible because just prior to the instant that one input has become 0, as the voltage at the base of Q1 is approximately 0.7 V and as Q2 and Q4 are in saturation, the voltage at the collector of Q1 is (Vσ2 + Vσ4) = 1.4 V.

Hence, the collector of Q1 is positive than its base by 0.7 V, which means that its base–collector diode is reverse-biased. Hence, Q1 is in the active region. This results in a large collector current in Q1 due to the normal transistor amplification. This current flows out of the base of Q2 and removes the stored charges quickly, thereby turning OFF Q2 and Q4 rapidly. As a result, the output goes to 1 level quickly, which accounts for the faster switching speed of the TTL gate. Q2 also switches ON faster when all the inputs go high. Therefore, TTL gate is considered as the fastest logic gate.

In Fig. 10.22(g), in place of the collector load RL for Q4, transistor Q3 and diode D3 are used as load (pull-up resistor, RL). This arrangement, where at the output of TTL gate one transistor is stacked on top of the other and their operation is complementary, i.e., when one transistor is ON (say Q3) the other is OFF (Q4) and vice-versa, is called a totem-pole arrangement. The advantage of totem-pole output circuits is that there is always one totem-pole transistor that is cut-off; except for a short time during the transition from one output state to the other. As a result, although the pull-up resistor is required, it can be much smaller than in the simple passive pull-up circuit. This reduces the time required to charge the input capacitance of gates connected to a totem-pole output due to the reduced time constant.

Totem-poles are the monumental sculptures carved from the great trees by native Americans. Standard (74/54 series) TTL has a fan-out of 10, propagation delay of 10 ns, power dissipation of 10 mW/gate and good noise immunity. The standard TTL logic gate with totem-pole output has a disadvantage in that the outputs of two gates can not be connected together to function as an AND gate. Consider the outputs of two such gates, shown in Fig. 10.23.

The two outputs are connected at A. Q4B acts as load for Q3A and in fact Q4B is a low-resistance load, hence, it draws a large load current ILoad. This may cause overheating of Q3A.

FIGURE 10.23 The TTL NAND gates with totem-pole output ANDed at A

TTL NOR Gates with Totem-pole Output. A TTL NOR gate with a totem-pole output is shown in Fig. 10.24. When both the inputs are V1 and V2 low, Q1A and Q1B are ON and Q2A and Q2B are OFF. Q3 is ON and Q4 is OFF. Hence, the output is 1. When both or any one of the inputs is 1, the output is low (0 level).

Open-Collector TTL Gates. The limitation in a standard TTL gate with totem-pole output is that the outputs can not be tied together. This can be overcome in an open-collector TTL gate. R4, D3 and Q3 that are there in a totem-pole circuit, as shown in Fig. 10.22 (g), are eliminated and Q4 has open-circuited the collector.

FIGURE 10.24 The TTL NOR gate totem-pole output

FIGURE 10.25 An open-collector TTL NAND gate

For this gate to work, an external pull-up resistor is connected from the collector of Q4 to VCC, as shown in Fig. 10.25.

The outputs of open-collector TTL gates can be connected together and the resultant arrangement is called a wired AND, as shown in Fig. 10.26. Q4,1, Q4,2 and Q4,3 are the output transistors of gates 1, 2 and 3.

When all the transistors are OFF, the output is 1. If anyone of the inputs is 0, the output is 0 (AND operation). This gate, however, has a lower switching speed.

Tri-state Logic Gates. In the logic gates seen till now the output is either high or low. The output has only two states. But in tri-state logic, in addition to the high and low states at the output, the gate circuit offers high output impedance. A tri-state (TSL) NAND gate with totem-pole output is shown in Fig. 10.27. This circuit is similar to the circuit shown in Fig. 10.22(g), except for the fact that a control input is connected through an inverter to one of the emitters (EC) of Q1 and through a diode D1, to the base of Q3.

FIGURE 10.26 The wired AND gate

FIGURE 10.27 The TSL NAND gate

Let the control input be low (0 V). The output of the inverter is high (5 V). Hence, D1 is reverse-biased and is an open circuit. The same high level (5 V) is connected to one emitter of Q1 (EC) which reverse-biases its base–emitter diode. Now, if both the inputs V1 and V2 are high, Q1 is OFF. Hence, Q2 is ON. Consequently Q3 is OFF and Q4 is ON. Thus, when all the inputs are high, the output is low.

When any or both the inputs are low, Q1 is ON and Q2 is OFF. Hence, Q3 is ON and Q4 is OFF. Hence, the output is at 1 level. We see that essentially the circuit behaves as a conventional TTL NAND gate when the control input is low.

If, on the other-hand, the control input is high, the output of the inverter is low. As a result, D1 is ON and a low level (0 V) is connected to the base of Q3. Hence, Q3 is OFF. At the same time, as a low level from the inverter is connected to EC, Q1 is ON, whatever may be the inputs to the gate terminals (V1 and V2). Therefore, Q2 is OFF and its output is high. Hence, Q3 should be ON and Q4 is OFF. However, Q3 is also OFF as a low level is connected to its base. Thus, both Q3 and Q4 are OFF when the control input is at 1level. The output of this gate thus, offers a high impedance to all the circuits connected to it, when the control input to the inverter is high. This is the third state of the TSL gate. The TSL gate allows the output to be high, low or offers high output impedance. Hence, the name tri-state logic gates.

Emitter-coupled Logic (ECL). The TTL gates considered till now have one major limitation-the ON device is driven into saturation resulting in a longer storage time. As a result, the switching speed is reduced. However, in emitter-coupled logic (ECL), also known as current mode logic (CML), the ON device is prevented from going into saturation, which ensures lesser storage time and faster switching speed. A typical OR/NOR gate is shown in Fig. 10.28.

A suitable voltage VBB is considered (This can be derived by using a potential divider network and also temperature compensation can be provided by using compensating diodes) such that there is a current IE(≈ IC3) in R1. This current can be adjusted so that Q3 is ON and in the active region.

When both the inputs V1 and V2 are low (0 V), Q1 and Q2 are OFF. The voltage at the collectors of Q1 and Q2 is VCC and is at 1 level (5 V), which is connected to the base of Q4. As Q4 is used as an emitter follower, this 1 level is transmitted to the output. The output of this emitter follower corresponds to the output of the NOR gate. At the same time Q3 is ON, the voltage at the base of Q5 is low and hence, the output of this emitter follower (OR) is low.

FIGURE 10.28 An emitter-coupled OR / NOR gate

When a high level (5 V), is connected to any one of the inputs (say, V1), then Q1 is ON. As a result, the voltage connected to the base of Q4 is low and the output of this emitter follower is low (NOR).

When Q1 is ON, there is larger current in R1 and a larger voltage drop in it. This reverse-biases the base–emitter diode of Q3, hence, Q3 is OFF. The voltage at the base of Q5 is high and the output of this emitter follower is high. Thus, if the output is taken at the emitter of Q4, this circuit is a NOR gate. And if the output is taken from the emitter of Q5, this circuit is an OR gate.

The major advantage of ECL gates is the smaller propagation delay as the devices are not allowed to saturate. However, at the same time, the resulting disadvantage is that the dissipation is larger as the ON device is held in the active region.

Integrated Injection Logic (I2L). Faster switching speed and low power dissipation are the two major factors that weigh favorably while choosing a logic gate. Apart from these, physical size and manufacturing costs could also be of concern as these gates are manufactured as integrated circuits. In an integrated circuit, transistors occupy ten times less space than the resistors. Thus, if transistors can replace resistors, then an appreciable reduction in the gate area can be achieved. Further, if the transistors Q1 and Q2 share common regions of n-type and p-type material, it is possible to achieve a greater circuit density.

The I2L gates eliminate the resistors. As n and p regions can be merged (alternately, transistors are merged), these logic gates are also called merged transistor logic (MTL) gates. Let us consider an RTL inverter, shown in Fig. 10.29.

In MTL logic, we want that R1and R2 should be replaced by two p–n–p transistors (as per the requirement of the current directions in Fig. 10.29) Q1 and Q3. Then the inverter circuit with transistors replacing resistors is redrawn as in Fig. 10.30

If Q1and Q3 supply the same currents I1 and I2, then R1 and R2 can be replaced by Q1and Q3. The currents I1 and I2 are injected into the transistor emitters. Hence the name integrated injection logic.

When the output of one inverter is connected as input to the next inverter, the transistor that supplies the base current to second inverter can become the collector load of the first inverter. As such, each inverter consists of only two transistors, as shown in Fig. 10.31. Here, we see that the base current for Q2 is supplied by Q1 (R1 shown in Fig. 10.29) and its collector current by Q3 (R2 shown in Fig. 10.29). Further Q3 also supplies the base current for Q4.

FIGURE 10.29 RTL inverter

FIGURE 10.30 Inverter with transistors

FIGURE 10.31 The two inverters connected in cascade

FIGURE 10.32 p and n regions are common for Q1 and Q2

In the manufacture of IC, if Q1 and Q2 share the common regions of p-type and n-type materials then these two transistors are said to be merged, as shown in Fig. 10.32.

As the base Q1 and the emitter of Q2 are n-type materials, a merged n-region (n1) is used for both. Similarly, the collector of Q1 and the base of Q2 are p-type materials, a merged p-region (p2) is used for both. The cross section of the above transistor gate is shown in Fig. 10.33.

By providing smaller currents I1 and I2, the power dissipation can be minimized. However, this accounts for a slower switching speed.

10.4.2 PMOS and NMOS Logic Gates

The major advantages of MOSFET devices are their very large input resistance, negligible power dissipation and a very small area for fabrication. Only FETS—no resistors, diodes or capacitors—are used. This is an example of direct coupled transistor logic (DCTL). We already know that an n-channel MOSFET is normally OFF when VGS = 0 and is ON when VGS is positive. Similarly a p-channel MOSFET is OFF when VGS = 0 and is ON when VGS is negative.

FIGURE 10.33 The cross-section of inverter where transistors replace resistors

p-channel MOSFETS are used in PMOS gates and n-channel MOSFETS are used in NMOS gates. These gates are similar except for the polarities of the supply voltages and direction of currents. However, NMOS gates are faster than PMOS gates because of the greater mobility of n-type charge carriers.

NMOS NAND Gates. NMOS NAND gate is shown in Fig. 10.34(a). The ON resistance, Ron of Q1 is typically 100 kΩ and that of Q2 and Q3 is of the order by 1 kΩ.

When both the inputs V1 and V2 are high (Q2 and Q3 conduct when the voltages at their gates are positive) Q2 and Q3 are ON. Q1 is also ON because its gate is tied to VDD. The resultant circuit is as shown in Fig. 10.34(b).

Hence, Vo is low. Consider the following cases:

  1. When V1 is low and V2 is high, Q2 is OFF, Q3 is ON and hence, Vo is high.
  2. When V1 is high and V2 is low, Q3 is OFF, Q2 is ON and hence, Vo is high.
  3. When V1 is low and V2 is low, Q2 is OFF, Q3 is OFF and hence, Vo is high.

Hence, the NMOS circuit as shown in Fig. 10.34(a) is a NAND gate Fig. 10.34(b). The circuit shown in Fig. 10.34(c) is an NMOS NOR gate.

FIGURE 10.34(a) An NMOS NAND gate

FIGURE 10.34(b) The resultant circuit when Q1, Q2 and Q3 are ON

When both the inputs V1 and V2 are low, Q2 and Q3 are OFF. Hence, the output is high. When both the inputs V1 and V2 are high, Q2 and Q3 are ON and the output is low but, when V1 or V2 is high, Q2 or Q3 is ON and the output is low.

FIGURE 10.34(c) A NMOS NOR gate

PMOS NAND and NOR gates are exactly similar to the NMOS counterparts except for the fact that the supply voltage is negative and the p-channel devices, which conduct when the gate voltage is negative, negative logic is employed.

PMOS NAND Gates. PMOS NAND gate is shown in Fig. 10.35(a). It is similar to its NMOS counter part except for the fact that the supply voltage is negative. It employs negative logic.

Q1 is ON as its gate is tied to −10 V

  1. When both the inputs V1 and V2 are 1 (= −10 V), Q2 and Q3 are ON. Vo = 0(= 0 V).
  2. When both the inputs V1 and V2 are 0 (= 0 V), Q2 and Q3 are OFF. Vo = 1(= −0 V).
  3. When V1 = 1 (= −10 V) and V2 = 0 (=0 V), Q2 is ON and Q3 is OFF. Vo = 1(=−10 V).
  4. When V1 = 0 (= 0 V) and V2 = 1 (= −10 V), Q2 is OFF and Q3 is ON. Vo = 1(= −10 V).

FIGURE 10.35(a) P-MOS NAND gate

The gate circuit in Fig. 10.35(a) is a NAND.

PMOS NOR Gates. PMOS NOR Gate is show in Fig. 10.35(b). Q1 is always ON as its gate is tied to −10 V

  1. When both the inputs V1 and V2 are 1 (= −10 V), Q2 and Q3 are ON. Vo = 0(=0 V).
  2. When both the inputs V1 and V2 are 0 (=0 V), Q2 and Q3 are OFF. Vo = 1(= −10 V).
  3. When V1 = 1 (= −0 V) and V2 = 0 (=0 V), Q2 is ON and Q3 is OFF. Vo = 0(=0 V).
  4. When V1 = 0 (=0 V) and V2 = 1 (= −10 V), Q2 is OFF and Q3 is ON. Vo = 1(= 0 V).

FIGURE 10.35(b) P-MOS NOR gate

The gate circuit in Fig. 10.35(b) is a NOR.

10.4.3 Complementary MOSFET Logic Gates

When two devices are identical in every respect, except for the polarity of voltages and current directions, they are called complementary devices. Therefore, two MOSFETS, one of which is a p-channel device and the other is an n-channel device, having identical parameters, are complementary devices. When these complementary devices are employed in a gate circuit the resulting gate is called a CMOS gate.

CMOS NAND Gates. Consider the CMOS NAND gate shown in Fig. 10.36(a). Here, Q1 and Q2 are PMOS devices and Q3 and Q4 are NMOS devices. Let us see the following conditions:

  1. When V1 and V2 are low (grounded):
    Here, the gates of Q1 and Q2 are negative with respect to the source terminals. Hence, Q1 and Q2 are ON as they are PMOS devices, whereas Q3 and Q4 are OFF as they are NMOS devices. Hence, the output is high, as shown in Fig. 10.36(b).

     

    V1 = V2 = 0,     Q1 and Q2 are ON, Q3 and Q4 are OFF, Vo = 1.

  2. When V2 is high and V1 is low:

    With V2 high, Q4 is ON and Q2 is OFF. However, with V1 low, Q3 is OFF and Q1 is ON. Therefore, the output is high, as shown in Fig. 10.36(c).

     

    V1 = 0, V2 = 1,     Q2, Q3 are OFF and Q1, Q4 is ON, Vo = 1.

  3. When V1 is high and V2 is low:

    With V1 high, Q3 is ON and Q1 is OFF. However, when V2 is low; Q4 is OFF and Q2 is ON. Therefore, the output once again is high, as shown in Fig. 10.36(d).

     

    V1 = 1, V2 = 0,     Q1 is OFF, Q2 and Q3 are ON and Q4 is also OFF, Vo = 1.

  4. When the inputs V1 and V2 are high:

    With V2 is high, Q2 is OFF and Q4 is ON. With V1 high, Q1 is OFF and Q3 is ON. Hence, the output is low, as shown in Fig. 10.36(e).

     

    V1 = 1, V2 = 1,     Q1 and Q2 are OFF, Q3 and Q4 are ON, Vo = 0

    FIGURE 10.36(a) A CMOS NAND gate

    Q1, Q2 — PMOS Devices

    Q3, Q4 — NMOS Devices

    FIGURE 10.36(b) The equivalent circuit when V1 and V2 are low

CMOS NOR Gates.

  1. CMOS NOR gate is shown in Fig. 10.37(a). Q1 and Q2 are p-channel devices and Q3 and Q4 are n-channel devices. Consider the following conditions: When V1 = 0 and V2 = 0:

    When V1 = 0, Q1 is ON and Q3 is OFF and when V2 = 0, Q2 is ON and Q4 is OFF then, Vo = 1, as shown in Fig. 10.37(b).

  2. When V1 = 0 and V2 = 1:

    FIGURE 10.36(c) The equivalent circuit when V1 is low and V2 is high

    FIGURE 10.36(d) The equivalent circuit when V1 is high and V2 is low

    FIGURE 10.36(e) The equivalent circuit when V1 and V2 are high

    FIGURE 10.37(a) A CMOS NOR gate

    Q1, Q2 — PMOS Devices

    Q3, Q4 — NMOS Devices

     

    When V1 = 0, Q1 is ON, Q3 is OFF and when V2 = 1, Q2 is OFF and Q4 is ON; then Vo = 0, as shown in Fig. 10.37(c).

  3. When V1 = 1 and V2 = 0:

    When V1 = 1, Q1 is OFF and Q3 is ON and when V2 = 0, Q2 is ON and Q4 is OFF; then Vo = 0, as shown in Fig. 10.37(d).

  4. When V1 = 1 and V2 = 1:

    When V1 = 1, Q1 is OFF and Q3 is ON and when V2 = 1, Q2 is OFF and Q4 is ON; then Vo = 0, as shown in Fig. 10.37(e).

FIGURE 10.37(b) The equivalent circuit when V1 and V2 are low

FIGURE 10.37(c) The equivalent circuit when V1 is low and V2 is high

FIGURE 10.37(d) The equivalent circuit when V1 is high and V2 is low

FIGURE 10.37(e) The equivalent circuit when V1 and V2 are high

CMOS devices must be handled properly as these can be destroyed by static electricity. The major advantage of CMOS is lesser power dissipation, larger fan-out and excellent noise immunity. The comparison of major IC logic families is shown in Table 10.6.

10.4.4 Interfacing of Logic Gates

When the output of a logic gate is required to drive another logic gate of a different family, then the logic 0 and 1 levels of the driving gate should be compatible with 0 and 1 levels of the driven gate, essentially because of the fact that the supply voltages of these two logic families could be different, also the currents could be different. This process of translation is called interfacing. Input and output voltage and current levels for standard TTL and CMOS logic gates are shown in Table 10.7.

When TTL Gate is Driving a CMOS Gate Operated with the same Supply Voltage. Supply voltage in both the cases is 5 V. Consider a TTL gate with totem-pole output driving a CMOS gate, as shown in Fig. 10.38(a). This is redrawn, representing the output of TTL gate driving the CMOS input shown in Fig. 10.38(b).

This is redrawn, representing the output of a TTL gate driving the CMOS input shown in Fig. 10.38(b).

We know that VOL(max) for TTL gate is 0.4 V and VIL(max) for a CMOS gate is 1.5 V. Hence, the logic 0 level is compatible. However, VIH(min) of CMOS gate (for 5 V supply) is 3.5 V i.e., VOH(min) of TTL is much smaller than VIH(min) of the CMOS gate. Hence, the TTL output must be raised to the acceptable level of CMOS and connecting a pull up resistor RC does this. When Q4 is OFF and VOH(min)VCC = 5 V, VIH(min) being 3.5 V, this satisfies the input requirement.

 

TABLE 10.6 A comparison of the performance of logic families

 

TABLE 10.7 The input and output voltages and current levels for standard TTL and CMOS logic gates

TTL Driving a CMOS Gate with 15 V Supply. From the Table 10.7, VIH(min) of CMOS 15 V gate is 11 V and VOH(min) of CMOS is 15 V. As the TTL output cannot be pulled to 15 V, an open collector buffer is used to interface the output of the TTL gate with a totem-pole output and a CMOS gate operating at 15 V as shown in Fig. 10.39.

Alternately, a dc-level translator can be used to interface the output of a TTL gate with the input of the CMOS gate operated at a higher voltage, as represented in Fig. 10.40.

FIGURE 10.38(a) A TTL gate driving a CMOS gate

FIGURE 10.38(b) A modified TTL gate driving CMOS gate

FIGURE 10.39 The logic gate interfacing the output of a TTL gate with a 15 V CMOS input

FIGURE 10.40 A TTL gate interfacing using a level translator

FIGURE 10.41 A CMOS gate driving a TTL gate

CMOS Gate Driving a TTL Gate. VOL of CMOS satisfies the VIL of a TTL gate. As the TTL input current is high and the CMOS output current is low, this may not be sufficient to drive the TTL gate. In such a case a buffer is used as an interface that can deliver the required TTL current as shown in Fig. 10.41.

SOLVED PROBLEMS

Example 10.6: Estimate suitable maximum logic 0 and minimum logic 1 input levels for the RTL gate in Fig.10.42 with VCC = 5 V, RC = 1kΩ, RB = 2kΩ and hFE = 20.

Solution: From Fig.10.42

VIH(min) = VBE + IIH(min)RB    VIH(min) = 0.7 + 0.24 × 10−3 × 2 × 103 = 1.18 V

VIL(max) = 0.2V

FIGURE 10.42 RTL gate with minimum high input and max low input voltages

Example 10.7: Determine the loading factor for the DTL gate in Fig.10.43 with hFE = 25 Assume that Germanium transistors and diodes are used.

FIGURE 10.43 DTL NAND gate output is connected to the one inputs of another gate

Solution: From the Fig.10.43

VA = VF4 + VF5 + VBE1 = 0.3 + 0.3 + 0.3 = 0.9 V

IB = I1I2 = 2.05 − 0.1 = 1.95 mA

IC1 = hFEIB = 25 × 1.95 × 10−3 = 48.75 mA

The maximum low level output current IOL = IC1I3 = 48.75 − 2.45 = 46.3 mA

When Q2 OFF, signal load current

Fan-out=Loading factor

Example 10.8: The wired AND gate is required to drive the inputs of three standard TTL gates, shown in Fig.10.44, which have Vcc = 5V. IIL(max) = 1.6 mA and IOL(max) = 16 mA and VOL(max) = 0.4 V. Determine a suitable pull-up resistance.

Solution: Total load current for three gates IL = 3 × IIL(max) = 3 × 1.6 mA = 4.8 mA Let us assume only one wired AND gate is ON

 

IRL = IOL(max)IL = 16 − 4.8 = 11.2 mA

VRL = VCCVOL(max) = 6 − 0.4 = 5.6 V

FIGURE 10.44 Wired AND gate

Example 10.9: Design a suitable interface circuit for CMOS, shown in Fig.10.45 with CDD = 5 V, driving two standard TTL gates with VCC = 5 V, hFE(min) of Q1 = 30 and RD(ON) = 1 kΩ. Given VIH(min) = 2 V, IIL(max) = 1.6 mA and IIH(max) = 40 μA.

FIGURE 10.45 Interface circuit for CMOS to drive two standard TTL gates

Solution:

The standard value is 33 kΩ

RB = 38.7 − 1 = 37.7 kΩ ≈ 33 kΩ (standard value)

SUMMARY
  • TTL gates operate with a supply voltage of 5 V whereas a CMOS gates operate with supply voltages ranging from 1 to 30 V.
  • VIH(min) of a gate is the minimum high-input voltage that represents a logic 1 level at the input.
  • VIL(max) of a gate is the maximum low-input voltage that represents a logic 0 level at the input.
  • IIH(min) of a gate is the minimum high-input current sufficient enough to drive the transistor into saturation.
  • IIL(max) is the maximum current that flows into an input when VIL(max) is applied as an input.
  • IOH(max) is the maximum high-level output current through the load and VOH(min) is the minimum output voltage for a logic 1 level.
  • IOL(min) is the minimum low-level output current through the load and VOL(max) is the maximum output voltage for a logic 0 level.
  • Fan-out of a gate is the number of inputs of the identical gates that a gate can drive.
  • Fan-in is the number of inputs of a gate.
  • Propagation delay is the time required for a gate to switch from a low-output state to a high-output state and vice-versa.
  • Noise immunity is the ability of the logic gate to tolerate changes at the input due to the noise but be still able to deliver the predictable output.
  • Power dissipation is the amount of power that is lost in heating the gate.
  • The figure of merit of a gate is the product of propagation delay and average power dissipation.
  • A tri-state logic gate allows the output to be low, high or offer high output impedance.
  • I2L or merged transistor logic (MTL) can provide larger circuit density as common regions of p-type and n-type are merged in fabricating the IC.
  • When the output of one logic gate is required to drive the input of another logic gate, the 0 and 1 levels of the driving gate should be compatible with the 0 and 1 levels of the driven gate. This process of translation is called interfacing of logic gates.
MULTIPLE CHOICE QUESTIONS
  1. The maximum number of inputs of many similar logic gates that any one gate output can drive is called:
    1. Fan-in
    2. Fan-out
    3. Noise immunity
    4. Noise margin
  2. The maximum number of inputs a logic gate has is called:
    1. Fan-out
    2. Fan-in
    3. Figure of merit
    4. Totem-pole output
  3. The time required for a logic gate to switch from a low output state to a high output state and vice-versa is called as:
    1. Propagation delay
    2. Rise time
    3. Transition time
    4. Turn-on time
  4. Noise immunity is normally specified as:
    1. Excellent or good or fair or poor
    2. 100 per cent
    3. 1/10 of the total noise
    4. None of the above
  5. NAND and NOR gates are called:
    1. Bidirectional gates
    2. Unilateral gates
    3. Universal gates
    4. High level logic gates
  6. A logic gate that allows the output to be 0, 1 or offers high impedance is called a:
    1. Tri-state logic gate
    2. NAND gate
    3. NOR gate
    4. DTL gate
  7. In an ECL gate, as the ON device is not driven into saturation, the advantage is:
    1. Lesser power dissipation
    2. Lower propagation delay
    3. Better noise immunity
    4. None of the above
  8. In I2L logic gates, as the transistors are merged, the major resultant advantage of this family is:
    1. Greater circuit density
    2. Better noise immunity
    3. Poor propagation delay
    4. Greater power dissipation
  9. CMOS gates are preferred because of their:
    1. Lesser power dissipation
    2. Faster switching speed
    3. Manufacturing process is simple
    4. Weight is less
  10. TTL gates are preferred because of their:
    1. Lesser power dissipation
    2. Faster switching speed
    3. Manufacturing process is simple
    4. Weight is less
  11. If the output of one family of logic gate is required to drive the input of another family of logic gate, 0 and 1 levels of the driving and the driven gate should be made compatible by a process of translation called:
    1. Interfacing
    2. Coupling
    3. Amplification
    4. Rectification
SHORT ANSWER QUESTIONS
  1. Explain how to calculate the propagation delay of a logic gate.
  2. What do you understand by the term noise immunity of a logic gate?
  3. Explain the terms high state noise margin and low state noise margin.
  4. What is meant by the figure of merit of a logic gate?
  5. Draw the circuit of a DTL NOR gate and explain its working.
  6. Draw the circuit of a DTL NAND gate and explain its working.
  7. What is meant by tri-state logic?
  8. What is the major advantage of an ECL gate?
  9. What is the major advantage of an I2L gate?
  10. Explain, in what respect, CMOS gates are preferred over TTL gates.
  11. Explain the process of interfacing the logic gates of different families.
LONG ANSWER QUESTIONS
  1. Draw the circuit of a TTL NAND gate with totem-pole output and explain its working. What is its main disadvantage?
  2. Draw the circuit of a TSL NAND gate and explain its working.
  3. Draw the circuit of an ECL OR / NOR gate. Verify its truth table.
  4. What is I2L logic? Explain how merging of transistors takes place in the manufacturing of this type of gate.
  5. Draw the circuits of PMOS NAND and NMOS NOR gates and verify their truth tables.
  6. Draw the circuits of CMOS NAND and NOR gates and explain their working with the help of the truth tables.
  7. Compare the performance of different logic families.
  8. What is meant by interfacing of logic gates? Suggest interfacing methods when:
    1. A TTL gate drives a CMOS gate with an operating voltage of 15 V.
    2. A CMOS gate with an operating voltage of 30 V drives a TTL gate.
UNSOLVED PROBLEMS
  1. Verify that the RLT gate in Fig.10p.1 is a NOR gate

    FIGURE 10P.1 RTL NOR gate

  2. (a)Verify that the circuit in Fig.10p.2 is a DTL positive NAND gate. Given VCC = V = 10 V, VBB = 10 V, RC = 2kΩ, R1 = 100 kΩ and hFE = 30; the input varies between 0 and 10 V. Neglect the junction voltages (b) Also determine the loading factor.

    FIGURE 10P.2 DTL Positive NAND gate

  3. The RTL gate shown in Fig.10p.3 has VCC = 9 V, VIL(max) = 0.2 V, VIH (min) = 2 V, IC(max) = 2 mA and hFE = 40. Calculate suitable resistance values for RB and RC.

    FIGURE 10P.3 RTL gate

  4. (a)Verify that the circuit in Fig.10p.4 is a DTL positive NOR gate. Given VCC = 10 V, VBB = 10 V, RC = 2kΩ, R1 = 100 kΩ, R2 = 200 kΩ and hFE = 20 and the input between 0 and 10 V. Neglect junction voltages. (b) Determine IOL, IIL and the loading factor.

    FIGURE 10P.4 RTL gate

  5. Determine IOL, IIL and the loading factor for the DTL gate in Fig.10p.5. Assume that silicon transistors and diodes are used. The transistors have hFE = 20.

    FIGURE 10P.5 RTL gate

  6. Design a suitable interface circuit for CMOS (see Fig.10p.6) with VDD = 15 V, driving three standard TTL gates with VCC =10 V, hFE(min) of Q1 = 30 and RD(ON) = 1 kΩ. Given VIH(min) =2 V, IIL(max) = 1.6 mA and IIH(max) = 40 μA.

    FIGURE 10P.6 RTL gate