# 11.3 Bidirectional Sampling Gates – Pulse and Digital Circuits

##### 11.3 BIDIRECTIONAL SAMPLING GATES

Till now we have considered gates that pass only unidirectional signals. Bidirectional sampling gates transmit both positive and negative signals. These gates can be derived using diodes, BJTs, FETs, etc. We are going to consider some variations of the bidirectional gates.

FIGURE 11.10 The unidirectional diode gate to transmit negative pulses

##### 11.3.1 Single-transistor Bidirectional Sampling Gates

A bidirectional sampling gate using a single transistor is shown in Fig. 11.11. The control signal and the input are applied to the base of Q. The control signal is a pulse whose amplitude varies between V1 and V2 and has a duration tp sufficient enough for a signal transmission. As long as VC is at the lower level V1, Q is OFF and at the output we only have a dc voltage VCC. However, when VC is at its upper level V2, Q is ON for the duration tp and if the input signal is present during this period, it is amplified and transmitted to the output with phase inversion but referenced to a dc voltage Vdc. At the end of tp, Q is again OFF and the dc voltage at its collector jumps to VCC. Thus, the signal is transmitted when the gating signal is at V2. However, the output contains a pedestal.

FIGURE 11.11 A bidirectional transistor gate

#### 11.3.2 Two-transistor Bidirectional Sampling Gates

The Fig. 11.12(a) shows another bidirectional transistor gate where two devices Q1 and Q2 are used and the control signal and the input signal are connected to the two separate bases.

There is no external dc voltage connected to the base of Q1, only the gating signal VC is connected. Let the control voltage be at its upper level, V2. Then, Q1 is ON and there is sufficient emitter current IE1 which results in VEN1 across RE. Q2 is biased to operate in the active region using R1 and R2. The voltage at the base of Q2 with respect to its emitter (VBE2) is (VBN2VEN1). If this voltage is sufficient enough to reverse-bias the base emitter diode of Q2, then Q2 is OFF. There is no output signal, but only a dc voltage VCC is available. However, when the gating signal is at its lower level V1, Q1 is OFF and Q2 operates in the active region and can also operate as an amplifier. If an input signal is present, there is an amplified output Vo. The presence of RE increases the input resistance Ri and thus, the signal source is not loaded.

From the waveforms shown in Fig. 11.12(b) it is seen that the output is VCC when Q2 is OFF. When the gating signal drives Q1 OFF and Q2 ON, the dc voltage at the collector of Q2 falls to Vdc (a voltage much smaller than VCC). During the period of the gating signal, the input signal is amplified and phase inverted by Q2 and is available at the output. Again at the end of the gating signal Q2 goes OFF and Vo jumps to VCC. Hence, the signal is superimposed on a pedestal.

FIGURE 11.12(a) A bidirectional transistor gate

FIGURE 11.12(b) The waveforms

#### 11.3.3 A Two-transistor Bidirectional Sampling Gate that Reduces the Pedestal

A circuit arrangement that reduces the pedestal is shown in Fig. 11.13. The control signals applied to the bases of Q1 and Q2 may have the same amplitude but are of a opposite polarity. When the gating signal is connected to Q1 at T = 0−, it is negative (at level V1). The net voltage at the base of Q1 is – (VBB1 + V1). Therefore, Q1 is OFF. At the same time the gating signal connected to Q2 is positive and is . The net voltage at the base of Q2 is (VBB2) and is positive and therefore, drives Q2 ON. Q2 draws a collector current IC. As a result, there is a dc voltage Vdc at its collector and Vo = Vdc. However, when the gating voltage at the base of Q1 drives Q1 ON and into the active region, at t = 0+, Q2 goes OFF as the gating signal is . During this period when Q1 is ON, if the input signal is present, it is amplified and is available at the output, with phase inversion. The bias voltages VBB1 and VBB2 are adjusted such that the quiescent current in Q1 and Q2 when ON is the same (= IC) and consequently the quiescent dc voltage at the output is Vdc. Therefore, the dc reference level practically is Vdc. At the end of the time period tp, Q1 once again goes into the OFF state and Q2 into the ON state and the dc voltage at the output is Vdc. As such the pedestal can be eliminated. However, our assumption is that the gating signals are ideal pulses (with zero rise time). In this case, the instant Q1 switches ON, Q2 switches OFF, as shown in Fig. 11.14(a). However, in practice the gating signals may not be ideal pulses but have a finite rise time and fall time; these may then give rise to spikes in the output shown in Fig. 11.14(b).

Let VBE be the voltage between the base and emitter terminals of a transistor when the device is in the active region. If the gating pulse is at its lower level (, negative), the net voltage as we have seen at the base of Q2 is far below the cut-off. As a result, Q2 goes OFF at t = t2. At the same instant, Q1 is required to go into the ON state, as the gating signal at its base is positive. However, because of the finite rise time associated with the gating signal at the base of Q1, it may not necessarily go into the ON state at the instant Q2 has gone into the OFF state (t2) and may go into the ON state at t = t1. The result is that the output is nearly VCC during the interval t2 to t1. This voltage, however, falls to Vdc when eventually Q1 is ON. A spike is developed at the output. Similarly, at the end of the gating signal Q1 goes OFF (at t = t4) before Q2 goes ON (at t = t3). Another spike develops at the output. It is seen that the gating signals themselves give rise to spikes in the output. If the rise time of the gating signal is large, these spikes are of larger duration as shown in Fig. 11.14(b), where as if the rise time of the gating signal is small, these output spikes are of smaller duration as shown in Fig. 11.15. If the rise time of the gating signal is small when compared to the duration of the gating signal, even though the spikes may occur in the output, as the duration of the signal is smaller than the spacing between the spikes, these spikes will not cause any distortion of the signal and hence, are not objectionable, as shown in Fig. 11.15.

FIGURE 11.13 Circuit that reduces the pedestal

FIGURE 11.14(a) There are no spikes in the output when the gating signals are ideal

FIGURE 11.14(b) The spikes of a longer duration if the rise time of the gating signal is large

#### 11.3.4 A Two-diode Bridge Type Bidirectional Sampling Gate that Eliminates the Pedestal

A bidirectional diode gate that eliminates the pedestal is shown in Fig. 11.16(a). R1, R1, D1 and D2 form the four arms of the bridge. When the control signals are at V1, D1 and D2 are OFF and no input signal is transmitted to the output. However, when the control signals are at V2, diode D1 conducts if the input (= Vs) are positive pulses and diode D2 conducts if the input are negative pulses. Hence, these bidirectional inputs are transmitted to the output. This arrangement because of the circuit symmetry eliminates a pedestal. Consider one half of the circuit that transmits the positive pulses to the output when D1 conducts (because of symmetry), as shown in Fig. 11.16(b).

FIGURE 11.15 The spikes of relatively smaller duration when the rise time of the gating signals is small

Thévinizing the circuit shown in Fig. 11.16(b) at node A, the Thévenin voltage source magnitude due to Vs (shorting VC source, considering one source at a time) and its internal resistance are calculated using the circuit shown in Fig. 11.16(c).

FIGURE 11.16(a) A bidirectional gate in the form of a bridge circuit

FIGURE 11.16(b) The circuit that transmits the positive pulses to the output

FIGURE 11.16(c) The equivalent circuit to calculate voltage at node A due to Vs source

FIGURE 11.16(d) The equivalent circuit to calculate voltage at node A due VC source

Similarly, Thevenizing the circuit shown in Fig. 11.16(b) at node A, the Thévenin source due to VC is (shorting Vs), shown in Fig. 11.16(d).

We have Rth1 = Rth2.

Redrawing the circuit shown in Fig. 11.16(b) and replacing the diode by its linear model (a battery of value Vγ in series with Rf, the forward resistance of the diode), results in the circuit shown in Fig. 11.16(e).

Similarly, considering the circuit when a negative signal is transmitted to the output when D2 is ON and combining the equivalent circuits of the two halves, we finally have the circuit shown in Fig. 11.16(f).

R3 = R + Rf, where R = Rth1 = Rth2

FIGURE 11.16(e) The equivalent circuit of the circuit shown in Fig. 11.16(b)

Rf is the diode forward resistance
Vγ is its cut-in voltage

We shall now define the gain of the transmission gate A (strictly speaking this is attenuation) as the ratio of Vo/Vs during transmission period. The control and small diode voltages do not contribute to any current in RL, the resultant simplified circuit is shown in Fig. 11.16(g). The open circuit voltage between P and the ground is αVs and the Thévenin resistance is R3/2, as shown in Fig. 11.16(h).

But

FIGURE 11.16(f) The equivalent circuit of Fig. 11.16(a)

Rf is the diode forward resistance
Vγ is its cut-in voltage

FIGURE 11.16(g) The simplified circuit of Fig. 11.16(f)

FIGURE 11.16(h) The circuit that enables the calculation of gain A

Therefore,

a) Minimum control voltage VC(min) required to keep both the diodes D1 and D2 ON: Let only the gating signals be present. The amplitude and polarity of the gating signals are such that both the diodes D1 and D2 conduct, and equal currents flow in these two diodes. When these equal and opposite currents flow in RL, the net voltage drop is zero and there is no pedestal.

Let Vs be a positive signal. As the amplitude of the signal goes on increasing, the current in D1 goes on increasing and that in D2 goes on decreasing. As Vs increases further, the current in D2 becomes zero (i.e., D2 is OFF). Thus, there is a minimum control voltage VC that will keep both the diodes ON. To calculate this VC(min), let it be assumed that D2 has just stopped conducting i.e., the diode current has become zero; the drop across R3 is zero. Therefore, the output voltage across RL is the open circuit voltage, as shown in Fig. 11.17(a).

FIGURE 11.17(a) The voltage Vo when D2 is OFF

FIGURE 11.17(b) The voltage Vo when D1 is ON

Now, calculating the output due to the left hand side signal source Vs and control signal (1 − α)VC, with the assumption that VγVs (i.e., Vr ≈0), as shown Fig. 11.17(b).

Eqs. (11.2) and (11.3) represent Vo hence,

αVsR3 = (1 − α)VC(R3 + 2RL)

VC(min) decreases with increasing RL.

b) Minimum control voltage Vn(min) to ensure that D1 and D2 are reverse-biased: We have calculated the minimum control voltage VC(min) i.e., needed to keep both the diodes, D1 and D2 ON. Similarly we calculate the minimum control voltage Vn(min) i.e., required to keep D1 and D2 OFF when no transmission takes place. If both the diodes are reverse-biased, the output voltage at point P is zero and P is at the ground potential, shown in Fig. 11.18(a). As D1 is reverse-biased, it behaves as an open circuit. As a result, the input appears at the output.

FIGURE 11.18(a) The gate circuit when D1 and D2 are reverse-biased

FIGURE 11.19(a) The bidirectional gate redrawn in the form of a bridge

VD1 = Voltage across D1 = [αVs + (1 − α)VC]

If Vn is the magnitude of VC at the lower level,

VD1 = [αVs + (1 − α)Vn]

For D1 to be OFF, VD1 must be either zero or negative. If VD1 is zero,

Therefore,

In practice VC(min) and Vn(min) are larger by 25 per cent. The bidirectional diode gate shown in Fig. 11.16(a) is redrawn as shown in Fig. 11.19(a). If the two control voltages are equal in magnitude but opposite in polarity the pedestal is not present in the output.

c) Input resistance: The purpose of the control signal is to enable the gate and the current drawn from the signal source does not depend on the control voltage. This current depends on the state of the diodes, whether they are ON or OFF. Here we assume that D1 and D2 as ideal diodes.

When the diodes D1 and D2 are OFF from Fig. 11.19(a) the equivalent circuit is as shown in Fig. 11.19(b) (obtained by open circuiting the diodes D1 and D2 and short circuiting VC sources). The input resistance is calculated using the circuit shown in Fig. 11.19(b).

(i) When D1 and D2 are OFF

FIGURE 11.19(b) The circuit of Fig. 11.19(a) when D1 and D2 are OFF

FIGURE 11.19(c) The circuit of Fig. 11.19(a) when D1 and D2 are ON

FIGURE 11.19(d) The simplified circuit of Fig. 11.19(c)

When the diodes are ON, the equivalent circuit is as shown in Fig. 11.19(c). The circuit of Fig. 11.19(c) after simplification is redrawn as shown in Fig. 11.19(d).

From the circuit in Fig. 11.19(d), input resistance Ri when the diodes are conducting is,

Now to calculate the gain of the transmission gate, A, let us calculate the Thévenin voltage source magnitude and its internal resistance. The circuit in Fig. 11.19(d) now reduces to that shown in Fig. 11.19(e).

FIGURE 11.19(e) The simplified circuit of Fig. 11.19(d)

Eq. (11.8) gives the expression for the transmission gain.

##### EXAMPLE

Example 11.1: In the circuit shown in Fig. 11.16(a), RL = R1 = 100 kΩ, R2 = 50 kΩ and the signal has a peak value of 20 V.

Find (a) A (b) VC(min) (c) Vn(min) (d) Ri when the diodes are ON

Solution:

1. Therefore,

2.

R3 = R + RfR = 33.3 kΩ

3. When the diodes are ON

= 20 + 50 = 70 kΩ

#### 11.3.5 Four-diode Gates

The main disadvantages with two-diode gates are (i) although A is called the gain, the circuit actually offers a large attenuation to the signal since A is small (much less than 1); (ii) the two control voltages VC and −VC should be equal in magnitude and opposite in polarity, failing which, there could be a pedestal in the output and (iii) Vn(min) can be appreciably large, as seen in Example 11.1. These limitations can be overcome in a four diode gate shown in Fig. 11.20(a). The differences seen in the four diode gate as compared to a two diode gate shown in Fig. 11.16(a) are (i) instead of connecting control signals at points A and B, sources + V and −V are connected at these points and (ii) the control signals are connected through the two additional diodes D3 and D4 to points P1 and P2.

FIGURE 11.20(a) A four-diode gate

When the control voltages are VC and –VC, D3 and D4 are reverse-biased and are OFF. However, D1 and D2 are ON because of + V and –V. The signal is connected to the load through R1 and the conducting diodes, as shown in Fig. 11.20(b).

When the signal is transmitted, as D3 and D4 are OFF, even if there is a slight imbalance in the two control voltages + VC and –VC, there is no pedestal at the output. Alternately, if the control voltages are at –Vn and Vn respectively, D3 and D4 conduct. As a result, D1 and D2 are OFF and now the output is zero. When D3 and D4 are OFF, the circuit is similar to a two diode gate and A is the same as given in Eq. (11.1) except for the fact that VC and –VC are replaced by V and –V. Also, the minimum value of voltage V(min) is the same as VC(min) in Eq. (11.4).

Therefore,

Let us now compute VC(min). If RfRL, for a positive Vs the voltage at P1 is AVs. If D3 is to be OFF, VC must at least be equal to AVs.

Vn(min) is calculated to satisfy the condition that D2 is OFF and D4 is ON. Then we calculate the voltage at the cathode of D4 (K2) due to sources –V and Vs using the superposition theorem, as shown in Fig. 11.20(c). The minimum voltage Vn(min) should at least be equal to VK2.

Therefore,

FIGURE 11.20(b) The circuit of Fig. 11.20(a) when D1 and D2 are ON and D3 and D4 are OFF

FIGURE 11.20(c) The circuit to calculate the voltage at the cathode of D4

##### EXAMPLE

Example 11.2: For the four-diode gate shown in Fig. 11.20(a), RL = R2 = 100 kΩ and R1 = 1 kΩ, Rf = 25 Ω, Vs = 20 V. Calculate (a) A (b) V(min) (c) VC(min) (d) Vn(min) for V = V(min)

Solution:

1. We have:

R3 = 990 + 25 = 1015 Ω

and

A = 0.985

2. VC(min) = AVs = 0.985 × 20 = 19.7 V
3. Here V = V(min) = 10.1 V Therefore,

From Example 11.2 it is evident that the additional diodes D3 and D4 improve A. Further during the transmission of the signal, D3 and D4 are OFF, thereby eliminating the pedestal that could be present in the output due to the possible imbalance in the two control voltages VC and –VC.

An alternate form of four diode gate is shown in Fig. 11.21(a). The differences between the gate circuit shown in Fig. 11.21(a) and that shown in Fig. 11.20(a) are (i) in the four diode gate shown in Fig. 11.21(a), the load RL is connected through a parallel path when all the diodes are conducting and (ii) there is no need for the sources + V and –V.

When the control signals are VC and −VC, D1, D2, D3 and D4 are ON. Considering only VC and −VC sources (Vs = 0), the resulting circuit can be redrawn as shown in Fig. 11.21(b). Redrawing the circuit shown in Fig. 11.21(b) the circuit that results is shown in Fig. 11.21(c). In this arrangement, VC/RC is the total current and VC/2RC is the current in each arm. Now, considering only the signal source Vs (VC = 0), the resultant circuit is shown in Fig. 11.21(d).

The voltages VC and –VC depend on the amplitude of Vs of the signal, which satisfies the condition that all the diodes are conducting i.e., the current flows in the forward direction. The net current in the diodes is due to the sources VC and Vs. The current in each diode due to the VC sources is VC/2Rc and is a forward current. On the other hand, the current due to the Vs source flows in the reverse direction in D3 and D2. The reverse current in D3 is Vs/2Rc + Vs/2RL and that in D2 is Vs/2RL. Thus, the reverse current in D3 is larger than the reverse current in D2.

For the diode D3 to be conducting, the forward current should be greater than the reverse current. We can, therefore, arrive at the minimum value of VC(VC(min)), when the forward current is equal to the reverse current.

FIGURE 11.21(a) Another form of the four-diode gate

FIGURE 11.21(b) The circuit when all the diodes are ON

FIGURE 11.21(c) The redrawn circuit of Fig. 11.21(b)

A balancing resistance R (divided symmetrically as R/2 and R/2) is included between D3 and D4 to give zero output for zero input. Then the sampling gate is as shown in Fig. 11.21(e).

If Rf and R are much smaller than RC or RL, then P1, P2, P3 and P4 are all at the ground potential, with Vs = 0, as shown in Fig. 11.21(f). If P1 is approximately at the ground potential,

FIGURE 11.21(d) The circuit shown in Fig. 11.21(c) with VC = 0

FIGURE 11.21(e) The four-diode gate with balancing resistance

FIGURE 11.21(f) The circuit of Fig. 11.21(e) when Vs = 0

Dividing by 4Rf

Since RfR

The larger reverse current in D3 (I2) is due to Vs (when VC = 0).

For VC to be VC(min), the forward current due to VC, i.e., I and the reverse current due to Vs, then I2 must just be equal.

Therefore,

If RRf, VC(min) becomes large and to calculate this value Eq. (11.15) may be used. If Rf and R are small as compared with RC and RL, the four diode gate during the transmission, can be represented as shown in Fig. 11.21(g). RS is the internal resistance of the signal source, Vs.

Considering the effective resistances of the parallel combinations the circuit shown in Fig. 11.21(g) reduces to that shown in Fig 11.21(h). So,

FIGURE 11.21(g) The four-diode gate during transmission

FIGURE 11.21(h) The simplified circuit of Fig. 11.21(g)

Multiplying both the numerator and the denominator by 4 we get,

Dividing the numerator and the denominator by 4RCRL we get,

If the diodes shown in Fig. 11.21(g) are to be OFF when the control voltages are Vn and –Vn, then,

##### EXAMPLE

Example 11.3: For the four diode gate shown in Fig. 11.21(a), Vs = 20 V, RL = 200 kΩ, RC = 100 kΩ, Rf = 0.5 kΩ, R = Rs = 1kΩ. Find Vn(min), A and VC(min).

Solution:

1. From Eq. (11.17), Vn(min) = Vs = 20 V
2. From Eq. (11.15),
3. From Eq. (11.16),

A = 0.963

From Examples 11.2 and 11.3 it is evident that the gain of the transmission gate is higher in a four-diode gate when compared to a two-diode gate.

#### 11.3.6 Six-diode Gates

For the four-diode gate shown in Fig. 11.20(a), the voltages + V and –V need to be large and have to be balanced to avoid pedestal. This gate circuit is insensitive to slight variations in the control voltages. Also, for the four diode gate [see Fig. 11.21(a)], the control voltages tend to become large and further there is a need for balanced control voltages, which is difficult. However, in the former case it is easy to choose large desired values for + V and –V and also easy to balance these two voltages as these are dc sources. For the circuit shown in Fig. 11.21(a), RL is connected through a parallel path with the result the current is shared by these two parallel branches. The transmission gain A in both the cases, however, is approximately unity. A six diode gate is shown in Fig. 11.22, and it combines the features of the gate circuits shown in Figs. 11.20(a) and 11.21(a).

When no signal is transmitted, D5 and D6 conduct while D1 to D4 remain OFF. During the transmission, D5 and D6 are OFF and this six diode gate is equivalent to the four diode gate seen in Fig. 11.21(a), earlier. If the diodes D5 and D6 remain OFF for the signal amplitude Vs, then,

The minimum required value of Vn is Vn(min) and is equal to Vs since the transmission diodes D1 to D4 will not conduct unless Vs exceeds Vn.

Hence,

The expression for A is given by Eq. (11.16).

FIGURE 11.22 A six-diode gate