11.4 FET Sampling Gates – Pulse and Digital Circuits


FET sampling gates can again be of two types: (i) a series gate and (ii) a shunt gate. The FET is simply used as a switch. In a series gate the FET switch is used as series element. Whereas in a shunt gate the FET switch is used as a shunt element. The advantage with FET and Op-amp sampling gates is that the input resistance is large and hence, the problem of loading is avoided.

11.4.1 FET Series Gates

The Fig. 11.23(a) shows a sampling gate where the switch is used as a series element. The practical switch can be an n-channel FET. FET series gate is essentially a voltage switch. [see Fig. 11.23(b)]

The input Vs, control signal VC and the output waveforms are shown in Fig. 11.23(c). The input Vs is a triangular wave, the control signal varies between V1 and –V2, and the output is either zero or varies as the input, depending on whether the FET is OFF or ON. The FET is ON (closed switch) when VC is V1 and is OFF (open switch) when VC is –V2.

A sampling gate is required to faithfully transmit the input signal to the output. For this to happen, the ON resistance of the FET, RD(ON) should ideally be zero and the drain current is kept at the minimum. Further Rs, the source resistance, should be very small when compared to RL, as shown in Fig. 11.24(a).

FIGURE 11.23(a) The FET series gate with (a) S as an ideal switch; (b) with FET as a switch

FIGURE 11.23(c) The waveforms of the series FET gate

If RsRL and RD(ON)RL

On the other hand, if the FET is OFF, the gate to source leakage current IGSS should be negligibly small. RC is normally large, typically of the order 1 MΩ, to make sure that IGSS is negligible, as shown in Fig. 11.24(b).

For the switch Q1 to be ON, the FET gate voltage VC should to be equal V1. Then as the FET is ON,


Vo = Vs and VC = V1 = Vs(peak).

Alternately for the switch Q1 to be OFF, the gate should be reverse-biased by approximately 1 V greater than the maximum VGS(OFF). Further,Vo =–Vs, the FET source terminal goes to negative peak of Vs. Therefore, to make sure that Q1 is OFF

FIGURE 11.24(a) The FET switch when ON

FIGURE 11.24(b) The FET switch when OFF

V2 = −(Vs(peak) + VGS(OFF)max + 1 V)

To understand the procedure to calculate the voltages needed to keep the switch ON and OFF let us consider an example.


Example 11.4: Consider the following situation in the FET series gate, Vs = ± 2 V, Rs = 100 Ω, RL = 10 kΩ. The FET has the following parameters:


VGS(OFF)max = −10 V and RD(ON) = 20 Ω.

Calculate the voltage levels of the control signal, ID, error due to RS and error due to RD(ON).


The control signal should have a value V1 for Q1 to be ON.

Therefore, V1 = Vs(peak) = 2 V

For Q1 to be OFF, the control signal should be –V2:


V2 = −(Vs(peak) + VGS(OFF)max + 1 V)

V2 = −(2 + 10 + 1) = −13 V

IDRS = 197 × 10−6 × 0.1 × 103 = 19.74 mV

IDRD(ON) = 197.4 μA × 20 Ω = 3.948 mV

11.4.2 FET Shunt Gates

When the source resistance RS is significantly smaller than RL then FET series gate is suitable. If RS is large, the condition that RSRL can not be satisfied, in such a case, FET shunt gate is more suitable. A shunt sampling gate is shown Fig. 11.25(a) and a shunt gate with an FET as a switch is shown in Fig. 11.25(b). The waveforms are shown in Fig. 11.25(c).

FIGURE 11.25(a) A shunt gate

FIGURE 11.25(b) The FET shunt sampling gate

When Q1 is OFF, there is a current IL in the load and an output is present. When Q1 is ON, the switch closes and the output is zero, as shown in Fig. 11.25(d).

Let us consider the situation when the FET switch is ON, as shown in Fig. 11.25(d).

If RD(ON) is the ON resistance of the switch, then Fig. 11.25(d) is redrawn as shown in Fig. 11.25(e). Now, there is a small VoIDRD(ON). Ideally Vo should be zero. Let us consider when the switch is open, as shown in Fig. 11.25(f).

ID(OFF) is the drain to source leakage current. Therefore,



As ID(OFF) is negligible, IL is expected to be IS. Thus, errors could be present in this type of sampling gate also.

FIGURE 11.25(c) The waveforms of an FET shunt sampling gate

FIGURE 11.25(d) When Q1 is ON

FIGURE 11.25(e) The FET switch when ON is replaced by RD(ON)

11.4.3 Op-amps as Sampling Gates

In the sampling gates seen till now, the signal is mostly attenuated during the transmission or some arrangements minimize attenuation. However, if the signal is to be amplified then an amplifier has to be provided. A FET controlled sampling gate employing an op-amp to amplify the signal is shown in Fig. 11.26(a).

The control signal VC is a train of negative pulses and the input signal Vs is a sinusoidal signal. Op-amp is used as an inverting amplifier. The waveforms are shown in Fig. 11.26(b). The gain of the op-amp inverting amplifier is AV = −R2/R1 when the FET Q1 is OFF.

When the FET is ON, the effective resistance in the feedback path of the op-amp inverting amplifier is R2 || RD(ON) which is negligibly small. Therefore, the output when Q1 is OFF is,

and the output when Q1 is ON is,

If RD(ON)R1, Vo ≈ 0.

FIGURE 11.25(f) When the FET gate is OFF

FIGURE 11.26(a) A FET controlled sampling gate using op-amp

FIGURE 11.26(b) The waveform of a sampling gate in which FET is used as a switch and op-amp as an inverting amplifier

The advantage of this sampling gate is that the signal may be amplified to a desired level. The output resistance is very low and the input resistance is R1. As such R1 can be appropriately chosen to have the desired input resistance.