# 16.2 Operational Amplifiers – Pulse and Digital Circuits

##### 16.2 OPERATIONAL AMPLIFIERS

An operational amplifier is a high gain direct-coupled amplifier, i.e, the output of one stage is directly connected to the input of the next stage. The advantage with a direct-coupled amplifier, essentially, is that it has a flat frequency response right from zero cycles. This means that operational amplifiers can be used for both dc and ac applications. An operational amplifier has four basic building blocks as shown in Fig. 16.1(a): (i) a dual-input, dual-output balanced differential or difference amplifier as the input stage; (ii) a dual-input, single-ended output, unbalanced differential amplifier as the voltage amplifier; (iii) dc-level shifter or level translator and (iv) the output power stage. Most of the gain of an op-amp is accounted for by the first stage. The output of this stage is taken between the two collectors of the differential amplifier and so the associated dc is practically zero at its output; and hence, the name balanced differential amplifier. The second stage is the differential amplifier, but the output is taken from one of the collectors. Hence, there is an associated dc component which could change the biasing for the next stage. Consequently the output could be distorted. Hence, there is a need for a dc-level shifter which translates the dc level and eliminates the distortion. Also in many applications, there is a need to reference the output to the zero level. The dc-level shifter ensures that the output is referenced to the zero level or to any desired dc level. The output power stage is normally a complimentary power amplifier to give the necessary power output. FIGURE 16.1 The basic building blocks of an op-amp

Ideally, an op-amp has the following characteristics:

1. The input resistance Ri is infinity.
2. The output resistance Ro is zero.
3. Open-loop gain is infinity.
4. vo = 0 when v1 = v2, i.e., the op-amp is balanced.
5. Bandwidth is infinity.

An operational amplifier is schematically represented as shown in Fig. 16.2(a) and the pin diagram of μA 741 is shown in Fig. 16.2(b)

The input stage of an op-amp is a differential amplifier. A practical differential amplifier is shown in Fig. 16.2(c). When bisected, one half of the circuit is a mirror image of the other. v1 and v2 are the two inputs to the differential amplifier. The output vo is taken between the two collectors. Let A1 be the gain of the first transistor and A2 the gain of the second. Then vo can be written as a linear combination of the two outputs: The differential signal is:  FIGURE 16.2(a) The schematic representation of an op-amp FIGURE 16.2(b) The pin diagram of op-amp μA 741 FIGURE 16.2(c) A practical differential amplifier

And the common-mode signal vc, which is an error signal is the average of the two input signals: or Solving Eqs. (16.2) and (16.3): and Putting Eqs. (16.4) and (16.5) in Eq. (16.1), we get: where, Ac = A1 + A2 = common-mode gain and Ad = = differential gain.

The output of this differential amplifier is given by Eq. (16.6). The common-mode component in the output is an error signal and the differential component is the desired signal. The goodness of a differential amplifier, i.e., how effective the amplifier is in rejecting the unwanted common-mode signal and in selecting only the desired differential signal, is expressed by its figure of merit known as the common-mode rejection ratio (CMRR). CMRR (indicated as ρ) is defined as Eq. (16.6) can be written as: Ideally, if ρ → ∞, then the output will only contain the differential component. For a practical differential amplifier, ρ should be as large as possible. In the open loop, the op-amp has a gain of infinity. This configuration is normally used in comparators, where the output is driven either to +VCC or to −VEE. However, to ensure that the op-amp is used as a linear circuit element, negative feedback must be provided in the amplifier.

#### 16.2.1 Some Applications of an Operational Amplifier

An op-amp is used for many applications. However, here we confine ourselves to only a few linear applications and study the switching applications.

Inverting amplifiers. Consider the amplifier circuit shown in Fig. 16.3(a) where the op-amp is used as an inverting amplifier (i.e., the output undergoes a phase shift of 180° when compared to the input).

If the op-amp is ideal, A = ∞ and Ri = ∞ As A → ∞, vi → 0.

This means that there exists a short circuit at the input terminals. Then the amplifier circuit is shown in Fig. 16.3(a) can be redrawn as shown in Fig. 16.3(b).

The circuit shown in Fig. 16.3(b) can be again redrawn as shown in Fig. 16.3(c). However, on the other hand, it is said that Ri = ∞, which means that there is an open circuit between the input terminals, shown in Fig. 16.3(d).

As a result, no current can flow through the input terminals. These are two contradictory requirements. If at all a short circuit exists at the input, the entire input current is expected to sink to the ground as there is seen to be a short circuit existing at the input terminals. However, as Ri = ∞, this current I, instead, flows through Rf. Thus, practically no short circuit exists between the input terminals of an op-amp, but it is seen to be existing because the voltage between the two input nodes is zero for all practical purposes (actually a very small voltage exists between the input terminals as the gain can not be infinity as ideally expected). We can say that there exists a virtual ground at the input of an op-amp. It is not a real ground or short circuit, however, for all practical purposes as A → ∞, vi → 0 and the voltage between the two input terminals is zero. This concept of virtual ground is used to calculate the gain with feedback. FIGURE 16.3(a) An op-amp as an inverting amplifier FIGURE 16.3(b) The short circuit at the input as A → ∞ FIGURE 16.3(c) The virtual ground at the input of op-amp FIGURE 16.3(d) An open circuit at the input as Ri = ∞

The circuit in shown in Fig. 16.3(c) is redrawn in Fig. 16.3(e). Thus, the gain of an inverting amplifier can be varied by adjusting Rf and R.

Non-inverting amplifiers. Now consider the circuit, shown in Fig. 16.4, called non-inverting amplifier, which means that the output and the input are in the same phase.

From Fig. 16.4:  FIGURE 16.3(e) The redrawn circuit of Fig. 16.3(c)

As there exists a virtual ground at the input, nodes 1 and 2 are at the same potential.

Therefore, v1 = vs.  FIGURE 16.4 A non-inverting amplifier

or Thus, the gain of the non-inverting amplifier is If in Eq. (16.11), Rf = 0 This means that the output is the same as the input, with the same magnitude and phase. The signal is transmitted faithfully to the output terminals. Hence, the amplifier is called a voltage follower and is used as a buffer amplifier.

Difference or Differential Amplifiers. The difference or differential amplifier produces an output that is proportional to the difference of the two input signals. However, as has been already mentioned, the output also contains an error term which is due to the common-mode signal which is the average of the two input signals. The error term can be minimized by employing an amplifier with large CMRR (ρ). Let us consider the difference amplifier circuit in shown in Fig. 16.5. If we bisect a difference amplifier, one half is the mirror image of the other, hence, the symmetric circuit.

From Eq. (16.6) we have the relation: Let us now calculate the output for the difference amplifier. From Fig. 16.5: v1 is due to the two sources vs1 and vo. Using the superposition theorem:  FIGURE 16.5 The circuit of a difference amplifier

Substituting Eqs. (16.14) and (16.15) in Eq. (16.13): Therefore, Consider the term in the denominator: since Substituting the Eq. (16.17) in Eq. (16.16), we have: If ρ = 100 dB, i.e., ρ = 105

The second term in Eq. (16.18) is negligible,

Therefore, The output of this amplifier as seen from Eq. (16.19) is proportional to the difference of the two input signals vs1 and vs2.

If vs2 = 0.2 mV and vs1 = 0.1 mV and R2/R1 = 100.

Then from Eq. (16.19):

vo = 100 × 0.1 mV = 10 mV FIGURE 16.6(a) An op-amp as a comparator FIGURE 16.6(b) The transfer characteristic

Comparators. A comparator is a circuit in which the output abruptly changes to a high level when the linear input voltage reaches an assigned reference value.

Consider the op-amp comparator as shown in Fig. 16.6(a). The reference voltage at the inverting input is VR. The transfer characteristic is shown in Fig. 16.6(b). When the input Vi reaches VR, the output Vo abruptly rises to V(sat) = VCC. When Vi > VR, Vo = +V(sat)(VCC ≈ 15 V, the positive supply voltage). Alternately when Vi < VR, Vo = −V(sat)(VEE ≈ −15 V, the negative supply voltage). The output thus jumps from +V(sat) to −V(sat) and vice versa when the input reaches VR, as shown in Fig. 16.6(c). FIGURE 16.6(c) The input and output waveforms of an op-amp comparator FIGURE 16.6(d) A zero-crossing detector

As we see in this comparator, the variation of the signal at the input has no resemblance to the output which is a pulse. This pulse can actuate a device.

Zero-crossing detectors. A zero-crossing detector is a special case of comparators. When the input voltage rises slightly above the zero level, the output swings to a high positive voltage (+VCC) and when the input voltage goes slightly below the zero level, the output switches to a large negative value (−VEE). The output is a pulse train with the frequency of the input signal. The leading edges and the falling edges of the pulses occur at the instants when the input crosses the zero level. The circuit of the zero-crossing detector is shown in Fig. 16.6(d).

When the input crosses the zero level and is slightly positive, the output of the op-amp differential amplifier Vo1 is +VCC (as the input is connected to the non-inverting terminal and the output and the input are in the same phase and the gain is large). This drives the transistor into saturation (ON). Therefore, the output Vo is −VEE + VCE(sat) ≈ −VEE. When the input is slightly below the zero level (negative), the op-amp output Vo1 is −VEE and the transistor is driven into the OFF state. The output voltage Vo is VCC. Thus, we see that the moment the input crosses the zero level, the output switches between the extreme values of VCC and −VEE. The circuit shown in Fig. 16.6(d) suggests that a comparator can be directly fabricated. The waveforms of the zero-crossing detector are shown in Fig. 16.6(e).

#### 16.2.2 Monostable Multivibrators

A monostable multivibrator using op-amp is shown in Fig. 16.7(a). D2 and D3 are Zener diodes with breakdown voltage VZ and D1 is an ordinary diode.

In the stable state (t < 0). Let us assume that an output voltage vo(= VD + VZVZ) is available. By using a potential divider network comprising R2 and R3, a feedback voltage v2 (= β vo = βVZ) is derived at the non-inverting terminal, where β = R3/(R2 + R3). As there exists a virtual ground at the input of an op-amp, v1 = v2 = β VZ. The capacitor C1 now tries to charge to βVZ. However, as D1 conducts since there exists a positive voltage at its anode with respect to the cathode; the voltage across the capacitor is held at VF (≈ 0.7 V for Silicon). Thus, in the stable state, the voltage across C1, VC1 remains at 0.7 V.

In the quasi-stable state (t = 0+). In the stable state voVZ, A negative pulse (trigger) is applied at the non-inverting terminal at t = 0+. The differential input is (v2v1). If V is the amplitude of the trigger then (v2v1) is (−V + 0.7), which is negative. As a result, the output suddenly swings from +VZ to −VZ, v1 = vi = −βVZ. D1 is OFF as the anode of D1 is negative. As a result, the capacitor C1 tries to charge from VF (= 0.7 V) to −VZ through R1, shown in Fig. 16.7(b). FIGURE 16.6(e) The waveforms of a zero-crossing detector

When the output is −VZ, the voltage v2 = −βVZ. The voltage across C1 tries to reach −VZ. The instant the voltage at the non-inverting terminal, v2(= −βVZ) is positive when compared to the voltage across C1 (voltage at the inverting input), the output swings to +VZ, D1 is ON and the voltage across C1 is again held at VF = 0.7 V, thus ending the quasi-stable state.

The waveforms are plotted as shown in Fig. 16.7(c). FIGURE 16.7(a) A monostable multivibrator using an op-amp FIGURE 16.7(b) The charging of C1 through R1 to −VZ FIGURE 16.7(c) The waveforms of a monostable multivibrator employing an op-amp

(iii) Calculation of the time period, T. The voltage variation across the capacitor C1 is given by:

vC1 = vf − (vfvi)et/τ    vf = −VZ, vi = VF       τ = R1C1

vC1 = −VZ − (−VZVF)et/τ

At t = T, If R2 = R3 then β = R3/(R2 + R3) = 0.5 and if VF << VZ, then T = 0.69 τ If in the above circuit, β = 0.5, R1 = 100 kΩ and C1 = 0.05 μF, T = 0.69 × 100 × 103 × 0.05 × 10−6 = 3.45 ms.

#### 16.2.3 Astable Multivibrators

An astable multivibrator employing an op-amp is shown in Fig. 16.8(a). The difference between the monostable circuit in shown in Fig. 16.7(a) and the astable circuit in shown in Fig. 16.8(a) is that the capacitor C and the diode D1 are eliminated and there is no need for an external trigger.

Let it be assumed that the circuit oscillates. Let initially the output be VZ at T = 0−, then vf = v2 = βVZ. The capacitor tries to charge to VZ. The feedback signal, v2 = βVZ. If the voltage across C1 (at the inverting terminal) is slightly more positive than v2 then at T = 0+, the output changes to −VZ, then v2 = −βVZ. The capacitor tries to charge to −VZ with the time constant τ = R1C1. When the voltage across the capacitor is slightly more negative than v2 = −βVZ, once again the output changes to +VZ. The feedback signal once again is v2 = βVZ. The capacitor once again tries to charge to +VZ and the process is repeated. The expressions for the time period can be obtained using the waveforms shown in Fig. 16.8(b).

The time period T1 can be calculated as follows:

vC1 = vf − (vfvi)et/τ        vf = −VZ, vi = +βVZ           vC1 = −VZ − (−VZβVZ)et/τ

At

t = T1 = T/2,

vC1 = −βVZ FIGURE 16.8(a) An astable multivibrator using an op-amp FIGURE 16.8(b) The waveforms of the astable multivibrator using an op-amp Therefore, If in the above circuit R1 = R2 = R3 = 100 kΩ, C1 = 0.2 μF T = 40 × 10−3 ln(3) = 43.94 ms and f = = 22.76 Hz FIGURE 16.9(a) An op-amp astable multivibrator FIGURE 16.9(b) The waveforms of vo and vC

#### 16.2.4 An Astable Multivibrator Using an Operational Amplifier Without Zener Diodes

A slight modification of the astable circuit is shown in Fig. 16.9(a) where the Zener diodes are eliminated. The output of the op-amp is now made to vary between +V(sat) (≈VCC) and −V(sat) (−VEE), resulting in a square-wave output.

Let the capacitor voltage initially be zero. Then the voltage v2 at the inverting input terminal is zero. Let the output offset voltage be V(sat).

Then where Thus, a small voltage v1 exists at the non-inverting input terminal. Hence, there exists a differential input vd = (v1v2). However, as the capacitor behaves as a short circuit initially, the gain of the amplifier, Ad is very large. Hence, the small differential input signal vd drives the output to +V(sat). Now the capacitor starts charging through R1 and when the voltage v2 is slightly more positive than v1, the output swings to −V(sat).

Then v1 = (−V(sat)) ×R3/(R3 + R2) = −αV(sat), which is negative. Hence, vd = (v1v2) is negative. Therefore, the output remains at −V(sat). The capacitor now begins to discharge. When the capacitor voltage is slightly more negative than −v1, vd becomes positive and the output once again is driven to +V(sat). When the output is +V(sat), The waveforms of vo and the capacitor voltage vC are shown in Fig. 16.9(b).

To calculate T1 and T2, from Fig. 16.9(b):

vC(t) = vf − (vfvi)et/τ

where τ = R1C

vf = +V(sat),      vi = −v1

vc(t) = V(sat) − (V(sat) + v1)et/τ

At t = T1,      vC(T1) = v1

v1 = V(sat) − (V(sat) + v1)eT1/τ

For a symmetric astable Using Eq. (16.24): Therefore, The frequency of oscillations is f = If R2 = 1.16 R3, then ln (2R3 + R2)/R2 ≈ 1.

Therefore,

T = 2τ      and      f = The slew rate of an op-amp defines the maximum time rate of change of the output under large signal conditions and is expressed in volts/seconds. The slew rate of an op-amp decides the highest frequency that can be generated. If the circuit is made to oscillate at still higher frequencies, the oscillator output becomes triangular. To avoid this problem resistances RS(= 100 kΩ or higher) are connected in series with the inverting and non-inverting terminals to avoid excessive differential current flow. Let us now consider an example.

##### EXAMPLE

Example 16.1: Design a square-wave generator using μA741 op-amp and supply voltages of ± 15 V to oscillate at 5 kHz.

Solution:

Given f = 5 kHz. R2 is chosen such that R2 = 1.16 R3. Choose R3 = 10 kΩ

Then,

R2 = 1.16 R3 FIGURE 16.9(c) An astable multivibrator with designed components

i.e., R2 = 11.6 kΩ

Use a 20 kΩ potentiometer. Choose C = 0.01 μF We know that, Hence, the desired circuit is as shown in Fig. 16.9(c).

#### 16.2.5 A Schmitt Trigger Using an Operational Amplifier

The Schmitt trigger circuit using discrete components with its hysteresis characteristic is discussed in detail in Chapter 9. A Schmitt trigger using op-amp 741 is shown in Fig. 16.10(a).

The transfer characteristic of a Schmitt trigger showing the hysteresis loop is shown in Fig. 16.10(b). A part of the output vo is fed back to the non-inverting input (v2) using the potential divider comprising R1 and R2. When v1 < v2, the voltage at pin 3 is greater than the voltage at pin 2. Therefore, the output is +V(sat) ≈ (VCC − 1 V) = 14 V.

If the input is increased further, when it is slightly greater than v2, the voltage at pin 2 is more than the voltage at pin 3, the output changes very rapidly to

−V(sat) ≈ −(VEE − 1 V) = −14 V  FIGURE 16.10(a) The Schmitt trigger using an op-amp FIGURE 16.10(b) The transfer characteristic of a Schmitt trigger

By adjusting R1 and R2, the desired values of UTP and LTP can be obtained. Example 16.2 elucidates the steps to design a Schmitt trigger.

##### EXAMPLE

Example 16.2: Design a Schmitt trigger circuit using 741 op-amp with a UTP = 5 V and LTP = −5 V. Use the supply voltage as ±15 V for 741. Given IB(max) = 500 nA

Solution:

If V2 is to be stable, I1 >> IB(max). If IB(max) = 500 × 10−9 A. Choose I1 = 100 IB(max)

100 × 500 × 10−9 = 50 μA         R1 = = 100 kΩ

Voltage across R2 is:

VR2 = vov2 = + V(sat)v2 = 14 − 5 = 9 V #### 16.2.6 Miller Integrator Time-base Generators Using Operational Amplifiers

Miller’s time-base circuit produces a linearly varying sweep voltage. Miller’s integrator time-base generator using an op-amp is shown in Fig. 16.11(a) and its waveforms are shown in Fig. 16.11(b).

Initially, let the voltage across C1 be zero. Then a negative trigger pulse is applied at the input and Q1, being an n-channel FET, is biased OFF by this negative trigger pulse. A current I1 flows in the direction shown in Fig. 16.11(a), charging the capacitor C1. Hence, the voltage across the capacitor increases linearly. When the trigger input switches to zero volts, Q1 is switched ON. The resistance between the drain and the source becomes very small and Q1 rapidly discharges C1. The next trigger pulse once again initiates a new sweep. If the discharging time (fly-back period) of C1 is to be very small (1/10 of the charging time, t), Q1 should be able to pass a current 10 times the charging current I1, during the discharge period. To ensure that Q1 is biased OFF when the input pulse is present, the input pulse must have a negative amplitude greater than the pinch-off voltage of the FET. Example 16.3 highlights method to design a Miller’s sweep generator. FIGURE 16.11(a) A Miller’s sweep generator FIGURE 16.11(b) The waveforms of a Miller’s sweep generator

##### EXAMPLE

Example 16.3: Design a Miller integrator sweep generator to generate an output of 5 V with a time period of 1ms and a discharge time of 50 μs. The FET has a pinch-off voltage of 6 V. Specify the input pulse and calculate the FET drain current.

Solution: We know that C1 is significantly larger than the stray capacitances (≈ 10 to 30 pF).

Select C1 = 1000 × 20 pF = 0.02 μF where, ΔV is the change in the output and t = capacitor charging time.

Therefore, Given that, |Vp(max)| = |VGS(off)| = 6 V. To ensure that Q1 is switched OFF, the magnitude of the trigger should be larger than the pinch-off voltage of the FET.

Select |vi| = Vp + 1 V = 6 V + 1 V = 7 V

The trigger should be negative with a magnitude of 7 V.

Then Let

R1 = R2 = 68 kΩ

The input pulse has vi = −7 V, pulse width = 1ms and space width = 50 μs #### 16.2.7 A Bootstrap Time-base Generator Using an Operational Amplifier

A bootstrap sweep circuit also produces a linearly varying sweep subject to satisfaction of the requirement that the amplifier used is an emitter follower with a large input resistance.

The circuit of a bootstrap sweep generator is shown in Fig. 16.12. This circuit has already been considered in Chapter 12 [see Fig. 12.16(a)].

In the bootstrap time-base generator, [see Fig. 12.16(a)] an emitter follower is used as an amplifier. For the sweep error to be small, the input resistance Ri is required to be large. Therefore, instead of an emitter follower, if an op-amp voltage follower is used, as shown in Fig. 16.12; because of its large input resistance, the sweep generator can produce a linearly varying sweep voltage.