17.8 Universal Gates – Pulse and Digital Circuits

17.8 UNIVERSAL GATES

AND and OR gates have a larger propagation delay and larger power dissipation when compared to NAND and NOR gates. Universal gates are the gates which can be used for implementing any gate such as AND, OR and NOT or any combination of these basic gates. The basic gates can be implemented by using either NAND gates or NOR gates. Hence, NAND and NOR gates are called universal gates. However, there are some rules that need to be followed when implementing either NAND- or NOR- based gates. Consider the NAND gate, shown in Fig. 17.19(a) and an OR gate with bubbled (inverted) inputs shown in Fig. 17.19(b). The outputs are same in both the cases, which means one can replace one gate by the other. Similarly consider the NOR gate, shown in Fig. 17.20(a) and an AND gate with bubbled (inverted) inputs shown in Fig. 17.20(b). Here again the outputs are the same in both the cases, which means one gate can be replaced by the other.

17.8.1 Implementing a NOT Gate Using NAND Gates

The NAND gate is shown in Fig. 17.21(a) and its truth table, is given in Table.17.25. From the truth table it is evident that if P is a logical 1, when Q = 0, f = 1 and when Q = 1, f = 0, which means that the output f is the complement of Q. So a NOT gate or an inverter is derived using a NAND gate by connecting P permanently to logic 1 as shown in Fig. 17.21(b). Alternatively, a NOT gate can also be implemented by using a NAND gate and tying, both the inputs to the same level instead of holding one input always at 1 as shown in Fig. 17.21(c).

FIGURE 17.21(a) A NAND gate

FIGURE 17.21(b) A NOT gate using NAND gate

 

TABLE 17.25 The truth table of the NAND gate

P Q f =
0 0 1
0 1 1
1 0 1
1 1 0

FIGURE 17.21(c) A NOT gate using a NAND gate

FIGURE 17.22(a) An AND gate using NAND gates

17.8.2 Implementing an AND Gate Using NAND Gates

An AND gate can be derived using NAND gates as shown in Fig. 17.22(a). An AND gate can also be implemented as shown in Fig. 17.22(b) using NAND gates.

FIGURE 17.22(b) An AND gate using NAND gates

17.8.3 Implementing an OR Gate Using NAND Gates

An OR gate using NAND gates is implemented as shown in Fig. 17.23(a). Alternatively, an OR gate can also be implemented using NAND gates as shown in Fig. 17.23(b).

FIGURE 17.23(a) An OR gate using NAND gates

17.8.4 Implementing a NOT Gate Using NOR Gates

A NOR gate is as shown in Fig. 17.24(a) and its truth table is given in Table 17.26. From the truth table, it is seen that if P is held at a logical 0, when Q = 0, f = 1 and when Q = 1, f = 0, i.e., the output f is the complement of Q (= ). Hence, a NOT gate using a NOR gate is obtained as shown in Fig. 17.24(b).

A NOT gate can also be implemented using a NOR gate and tying both the inputs to the same level instead of holding one input always at 0 as shown in Fig. 17.24(c).

17.8.5 Implementing an AND Gate Using NOR Gates

Consider the arrangement shown in Fig. 17.25. This is an AND gate using NOR gates. An AND gate can also be realized using a NOR gate as shown in Fig. 17.26.

17.8.6 Implementing an OR Gate Using NOR Gates

An OR gate can be obtained by using NOR gates as illustrated in Fig. 17.27. An OR gate can also be realized by using a NOR gate as shown in Fig. 17.28.

TABLE 17.26 The truth table of a NOR gate

P Q f =
0 0 1
0 1 0
1 0 0
1 1 0

FIGURE 17.23(b) An OR gate using NAND gates

FIGURE 17.24(a) A NOR gate

FIGURE 17.24(b) A NOT gate using a NOR gate

FIGURE 17.24(c) A NOT gate using a NOR gate

FIGURE 17.25 An AND gate using NOR gates

FIGURE 17.26 The realization of an AND gate using a NOR gate

FIGURE 17.27 An OR gate using the NOR gate

FIGURE 17.28 The realization of an OR gate using NOR gates

17.8.7 The Exclusive OR Gate

An exclusive OR gate excludes the OR operation for an even number of high inputs and in the remaining conditions it is the same as an OR gate. An exclusive OR (Ex-OR) gate has the Boolean relation:

f = Q + P and is expressed as,

f = P Q.

The truth table for an Ex-OR gate is given in Table.17.27. The exclusive OR gate is schematically represented as shown in Fig. 17.29.

 

TABLE 17.27 The truth table of an Ex-OR gate