18.2 Flip-flops – Pulse and Digital Circuits

18.2 FLIP-FLOPS

The bistable multivibrator is generally termed as a flip-flop. Flip-Flop is a one-bit memory element. A flip-flop can be triggered symmetrically (synchronously) or unsymmetrically (asynchronously). Various variations in flip-flops are considered here.

18.2.1 The Basic RS-latch

An RS-latch is the simplest possible memory element. It is constructed by feeding the outputs of NOR gates back to the input of the other NOR gates. These cross connections act as feedback, as shown in Fig. 18.3.

The inputs R and S are referred to as the Reset and Set inputs, respectively. To understand the operation of the RS-latch, consider the following cases: For the NOR gate when any one of the inputs is 1 the output is 0. The outputs Q and are complement to each other.

  1. If S = 1 and R = 0, the output of the second NOR gate is zero, i.e, = 0. Hence, both the inputs to the first NOR gate are zero. Hence, Q = 1. Therefore, the input combination S = 1 and R = 0 leads to the RS-latch being set to Q = 1.
  2. If S = 0 and R = 0; and as Q = 1 the output of the second NOR gate is 0. The inputs to the first NOR gate now are 0 and 0. Hence Q = 1 and = 0. This implies that the RS-latch remains in the same state (hold state).

    FIGURE 18.3 The basic RS-latch using NOR gates

    TABLE 18.1 The operation of RS-latch

    FIGURE 18.4 The timing diagram of the RS-latch using NOR gates

  3. If S = 0 and R = 1; and as Q = 1, the output of the second NOR gate = 0. Now the inputs to the first NOR gate are 0 and 1. Hence, Q = 0. Therefore, the input combination S = 0 and R = 1 leads to the RS-latch being set to Q = 0.
  4. S = 1 and R = 1 implies that both Q and are 0 which is unacceptable. This input combination must be avoided. It is called the race-away condition.

Since the memory element goes to a ‘0’ state or reset state when R = 1 and to ‘1’ state or set state when S = 1, it is called an RS-latch. The operation of the RS-latch is summarized in the Table 18.1.

To understand the operation of the RS-latch, let us assume that the output Q = 1 and = 0. Q and S are the inputs to the gate 2 and and R are the inputs to the gate 1. As per the initial assumption both the inputs to gate 2 are low then the output of gate 2 is 0. i.e., = 0. The inputs to the gate 1, = 0 and R = 0 then the output of the gate 1, Q is 1. The outputs remain the same as in the previous condition i.e., no change in the outputs. Both Q and are zero and is not an acceptable condition. Fig. 18.4 shows the timing diagram and is explained with the help of Table 18.2. An RS-latch can also be constructed from NAND gates.

18.2.2 The SR-latch Using NAND Gates

The logic symbol of an SR-latch is shown in Fig. 18.5(a). The set–reset or SR-latch is also named as set-clear flip-flop. Here, the SR latch is designed using NAND gates, which operates on negative pulses for triggering, as shown in Fig. 18.5(b). For the NAND gate, when any one of the inputs is 0, the output is 1. Consider the inputs S and R and the corresponding outputs Q and . The working of an SR flip-flop is explained below.

 

TABLE 18.2 The truth table of RS-latch using the NOR Gates at different time instants

FIGURE 18.5 The RS-latch using the NAND gate

Let it be assumed arbitrarily that initially Q = 1 and = 0. Then the inputs to gate 2 are R and Q. If R = 1 and as Q = 1, the output of gate 2 is 0. The two inputs to gate 1 are S = 1 and as = 0. Hence, the output Q of gate 1 is 1. Thus, at t = t1, Q = 1 and = 0. Let us now consider the situation at various time instants t1 to t10 from the input waveforms (S and R). Fig. 18.5(c) shows the timing diagram and is explained with the help of the Table 18.3.

 

TABLE 18.3 The truth table of the SR flip-flop at different time instants

FIGURE 18.6 The positive edge triggered SR-flip-flop: (a) positive pulse triggered RS flip-flop logic symbol; (b) RS flip-flop using NOR Gates; and (c) the timing diagram

18.2.3 Positive Pulse Triggered SR Flip-flops

A positive pulse triggered SR flip-flop is shown with its timing diagram in Fig. 18.6. It is asynchronous. Initially, at t = 0, let Q = 1 and = 0. Here, NOR gates are used to implement the flip-flop.

18.2.4 Clocked SR Flip-flops

To the basic RS-latch if an external clock pulse is given as shown in Fig 18.7, the circuit becomes a clocked SR flip-flop. If the clock pulse (CLK) is 0, the outputs of AND gates 1 and 2 are 0;hence, the inputs to NOR gates 1 and 2 are equal to 0. Therefore, when CLK is zero, the flip-flop remains in the same state. When CLK = 1 then R act as the input to the NOR gate 1 and S is the input to the NOR gate 2. Let us define Q(t +) as the state to which the flip-flop would go after the occurrence of CLK. This state depends on the present state of the flip-flop Q and the external inputs, R and S. So, if we tabulate the results for all the combinations of inputs and the present state of the flip-flop, this table is known as the characteristic table, given in Table 18.4. From the characteristic table, we find the minimal solution of Q (t +), using the K-map given in Table 18.5. Therefore, from the K-map given in Table 18.5:

To avoid the race away condition:

Equations (18.1) and (18.2) are together known as the characteristic equation of the clocked RS flip-flop which specifies the complete operation of the flip-flop. The operation of a NAND gate flip-flop is dual to that of a NOR gate. A clocked SR flip-flop using NAND gates and its timing diagram are shown in Fig. 18.8. Table 18.6 and the timing diagram clearly explain the working of this flip-flop.

FIGURE 18.7 The clocked SR flip-flop

TABLE 18.4 The characteristic table of the clocked RS flip-flop

TABLE 18.5 The K-map for clocked RS flip-flop

Here, only when any of the inputs S or R is 1 (the other being 0) and the clock (CLK) is 1, Q changes its state. The clocked SR flip-flop is used to facilitate synchronous operation. The circuit response can be controlled by adding the clock signal to the circuit. It means that the outputs will respond to the input levels only during the active period of a clock signal. To illustrate the operation of the clocked SR flip-flop, clock (CLK), S, R waveforms and the outputs Q and are shown in Fig. 18.8.

Initially, i.e., at t = (0−), assume the flip-flop is in its clear state with Q = 0 and Q(t+) = 0. is the complement of Q. From the timing diagram shown in Fig. 18.8(c) and the Table 18.6, it is seen that the outputs change their state only when the clock input goes from 0 to 1. If the inputs are S = 1 and R = 0 with CLK being active high the inputs to the basic SR-latch S1 = 0 and R1 = 1. When S1 = 0 and R1 = 0, the latch goes to the set state, then the output changes to the set condition (Q(t+) = 1, (t+) = 0). When CLK is low, the output remains in the set condition even though the input S changes from 1 to 0. If the inputs are S = 0 and R = 1 with CLK being active high the inputs to the basic SR-latch, S1 = 1 and R1 = 0, the latch goes to the next state, then the outputs change to the reset condition (Q(t+) = 0, (t+) = 1). If both the inputs are 0 then there is no effect by the clock and the flip-flop continues to remain in the previous state. If both the inputs are at 1 with CLK high then the flip-flop goes to the forbidden state or race-away condition which is unacceptable, as given in Table. 18.6. The disadvantage with the clocked RS or SR flip-flop is the race-away condition. This can be avoided by providing a feedback path.

FIGURE 18.8 The clocked SR flip-flop: (a) clocked RS flip-flop logic symbol; (b) RS flip-flops using NAND gates with active high inputs; and (c) the timing diagram

TABLE 18.6 The truth table of clocked SR- flip-flop at different time instants

18.2.5 JK Flip-flops

A clocked SR flip-flop has the disadvantage that S = R = 1 is not an acceptable condition because the flipflop goes into an indeterminate state. This problem is eliminated in a JK flip-flop. Here, the earlier two-input NAND gates in an SR flip-flop are replaced by three-input NAND gates. J and K are the inputs to these NAND gates apart from the clock input. The third input to each of these NAND gates is derived as the feedback from Q and . The logic symbol and gate-level implementation of the JK flip-flop are shown in Fig. 18.9.

Let the flip-flop be initially in its CLEAR state i.e., Q = 0 and = 1. Let us assume that CLK = 1. For a NAND gate, if any one of the inputs is 0, the output is 1. If CLK = 0, immaterial of the states of J, K, Q and , the inputs to the basic NAND RS-latch are both 1s, which implies that the flip-flop continues to remain in the same state (CLEAR state).

FIGURE 18.9 The JK flip-flop: (a) JK flip-flop logic symbol; (b) gate-level schematic of the clocked NAND-based RS flip-flop; and (c) gate-level implementation of the clocked JK flip-flop

Let the inputs to the JK flip-flop be J = 0 and K = 0. Then:

 

(a) The inputs to the NAND gate 1 are J = 0, = 1, CLK = 1; therefore, the output is 1 which is the input to the NAND gate 3.

(b) The inputs to the NAND gate 2 are K = 0, Q = 0, CLK = 1; therefore, the output is 1 which is the input to NAND gate 4.

(c) Both the inputs to the basic NAND RS-latch are 1s, which implies that the flip-flop continues to remain in the same state (CLEAR state).
If J = 1 and K = 1, Q = 0 and = 1, then

(a) The inputs to the NAND gate 1 are J = 1, = 1, CLK = 1; therefore, the output is 0, which is the input to NAND gate 3.

(b) The inputs to the NAND gate 2 are K = 1, Q = 0, CLK = 1; therefore, the output is 1, which is the input to NAND gate 4.

(c) The inputs to the basic NAND RS-latch are S = 0 and R = 1, which implies the flip-flop goes to the SET state, i.e., Q = 1 and = 0.
If J = 1 and K = 1 Q = 1 and = 0, then

(a) The inputs to the NAND gate 1 are J = 1, = 0, CLK = 1; therefore, the output is 1, which is the input to NAND gate 3.

(b) The inputs to the NAND gate 2 are K = 1, Q = 1, CLK = 1; therefore, the output is 0, which is the input to NAND gate 4.

(c) The inputs to the basic NAND RS-latch are S = 1 and R = 0 which implies the flip-flop goes to the reset state.

Thus, even if J and K are both equal to 1, the flip-flop will not go into the indeterminate state because of the feedback. Thus, the race-away condition can be eliminated. The operation of the JK flip-flop is shown in its characteristic table given in Table 18.7(a).

The contents of the characteristic table are mapped on to the K-map as given in Table 18.7(b). From the K-map, the characteristic equation of JK flip-flop is:

TABLE 18.7(a) The characteristic table of a JK flip-flop

TABLE 18.7(b) The K-map of a JK flip-flop

TABLE 18.7(c) The truth table of a JK-flip-flop at different time instants

The timing diagram is shown in Fig. 18.10. The working of a JK flip-flop is understood with the help of the timing diagram and its truth table as is shown in Table.18.7(c).

From the timing diagrams and the truth table, it is evident that when J = 1 and K = 0 and CLK = 1, the output goes to the set condition (Q = J = 1). When J = 0, K = 1 and CLK = 1, the output goes to reset ( = K = 1).

FIGURE 18.10 The timing diagram of a JK flip-flop

When J = K = 1 and CLK = 1, the output toggles, i.e., the output at tn is complemented at tn+1.J = K = 0 is an inhibited condition, i.e., no change in the output takes place.

At t1, the clock input goes from 0 to 1 and this triggers the flip-flop, at this moment the control inputs are J = 1 and K = 0 then the outputs are changed to Q = J = 1, = K = 0. Thus, At t3, the clock input again goes from 0 to 1 and this triggers the flip-flop, at this moment the control inputs are J = 0 and K = 1, then the outputs are changed to Q = J = 0. Thus, = K = 1. At t5, t7 the clock input goes from 0 to 1 and this triggers the flip-flop, at this moment the control inputs are J = 1 and K = 1 then, the outputs of the flip-flop toggles from one state to the other, every time the clock input goes from low to high.

18.2.6 D Flip-flops

A clocked SR flip-flop has two inputs S and R and a clock input. However, a D flip-flop has only one input (D or Data input) and a clock input. In a clocked SR flip-flop, when both S and R are 1, the flip-flop goes into the indeterminate state. This condition is avoided in a D flip-flop as the S input is inverted and connected to R. When the flip-flop is triggered by the CLK signal, then the output is at the level of the D input. It means that the input data is available at the output when the flip-flop is triggered by the clock signal. So this is called the data flip-flop.

Fig. 18.11(a) shows the logic symbol of the D flip-flop. Fig. 18.11(b) shows the D flip-flop derived from the SR flip-flop and Fig. 18.11(c) shows the gate-level implementation. To illustrate the operation of a D flip-flop, a simple clock (CLK), D input and output waveforms (Q and its complement) are shown in the timing diagram in Fig. 18.11(d).

When D input is 1, the output Q(t+) changes to 1, when CLK changes from low to high. Q changes to 0, when D = 0 with the CLK high.

FIGURE 18.11 The D-flip-flop (a) D flip-flop logic symbol; (b) D flip-flop operated by an RS flip-flop; (c) gate-level schematic of the D flip-flop; and (d) the timing diagram

TABLE 18.8 The truth table of D flip-flop at different time instants

The working of the D flip-flop is understood with the help of the timing diagram and its truth table is as in Table.18.8. Thus, in a D flip-flop, when D changes from 0 to 1 or from 1 to 0 and if the clock input is 1, Q(t +) changes. However, if the clock input is 0, there is no change in the output. Hence, when CLK is 1, irrespective of Q, the next state, i.e., the state after the occurrence of CLK Q (t +) is D. Therefore, it is known as a data transfer flip-flop or D flip-flop.

18.2.7 T Flip-flops

Fig. 18.12(a) shows the gate-level implementation of a T flip-flop and Fig. 18.12(b) shows the logic symbol of the positive edge triggered T flip-flop. The timing diagram and the truth table help in understanding the working of this flip-flop. The outputs Q and change when T input changes from low to high, i.e., at the positive edge of the trigger signal.

Let the flip-flop be initially in its CLEAR state, i.e., Q = 0 and = 1. And let us assume that CLK = 1. For a NAND gate, if any one of the inputs is 0, the output is 1. If CLK = 0, immaterial of the states of J, K, Q and , the inputs to the basic NAND RS-latch are both 1s, which implies that the flip-flop continues to remain in the same state (CLEAR state).

Let the input to the T flip-flop be T = 0, then:

 

(a) The inputs to the NAND gate 1 are T = 0, = 1, CLK = 1; therefore, the output is 1, which is the input to NAND gate 3.

(b) The inputs to the NAND gate 2 are T = 0, Q = 0, CLK = 1; therefore, the output is 1, which is the input to NAND gate 4.

(c) Both the inputs to the basic NAND RS-latch are 1s, which implies that the flip-flop continues to remain in the same state (CLEAR state).
If T = 1, Q = 0 and = 1, then:

(a) The inputs to the NAND gate 1 are T = 1, = 1, CLK = 1; therefore, the output is 0, which is the input to NAND gate 3.

FIGURE 18.12 The T Flip-flop: (a) gate-level implementation of clocked T flip-flop; (b) the logic symbol; and (c) the timing diagram

(b) The inputs to the NAND gate 2 are T = 1, Q = 0, CLK = 1; therefore, the output is 1, which is the input to NAND gate 4.

(c) The inputs to the basic NAND RS-latch are S = 0 and R = 1, which implies that the flip-flop goes to into the set state.
If T = 1 Q = 1 and = 0, then:

(a) The inputs to the NAND gate 1 are T = 1, = 0, CLK = 1; therefore, the output is 1, which is the input to NAND gate 3.

(b) The inputs to the NAND gate 2 are T = 1, Q = 1, CLK = 1; therefore, the output is 0, which is the input to NAND gate 4.

(c) The inputs to the basic NAND RS-latch are S = 1 and R = 0, which implies the flip-flop goes to the reset state.

So in a T flip-flop state the transition takes place when T = 1. The timing diagram and transition table are shown in Fig. 18.12(c) and Table 18.9.

 

TABLE 18.9 The truth table of positive edge triggered T- flip-flop at different time instants

18.2.8 Master–Slave Flip-flops

The disadvantage with the flip-flops which are triggered during the occurrence of the clock pulses is that if there are frequent changes in the input during the duration of the clock pulse the flip-flop may not be able to respond to these changes and this may lead to instability. One way to avoid this situation is by making the flip-flop respond to the rising edge or falling edge of the clock pulse. If the flip-flop responds to the rising edge, it is said to be a positive edge triggered; and if it responds to the falling edge, it is said to be a negative edge triggered. For example, if it is a positive edge triggered flip-flop, then the flip-flop responds to the changes in the input only when the clock pulse rises from 0 to 1. The other way to avoid this instability is by creating a delay. This can be done by using a master–slave flip-flop. The master–slave flip-flop consists of two flip-flops—one is a master and the other a slave. The master responds during the positive pulse and the slave responds during the negative pulse. Any of the above discussed flip-flops can be used for the master and slave. The master–slave flip-flop is given the name according to the type of flip-flop used for the master. If the master is an RS flip-flop it is called as a master slave RS flip-flop. Let us consider a master–slave flip-flop whose master is an RS flip-flop and the slave is also an RS flip-flop.

Fig. 18.13(a) shows a master–slave RS flip-flop where the master is a clocked RS flip-flop triggered by the positive clock pulse and the slave is also a clocked RS flip-flop triggered by the negative clock pulse. The output of the master would be the input to the slave, when the clock is negative. Fig. 18.13(b) represents the timing diagram and Table 18.10 is its truth table.

The master is triggered during the positive clock pulse and the slave is triggered during the negative clock pulse. The output of the master flip-flop at the end of the positive clock pulse is the input to the slave flip-flop during the negative clock pulse. Let Y and be the outputs of the master flip-flop at the end of the positive pulse. Therefore, during the negative clock pulse the inputs to the slave will be Y and . Let initially the flip-flop be in its clear state, i.e., the output Y and Q are equal to 0. When t = 0, i.e., the first positive clock pulse, the master is triggered. The inputs to the master are R = 1 and S = 0. Therefore, the flip-flop goes to its reset state with Y = 0 and = 1. During the negative clock pulse, i.e., at the instant t0, the slave is triggered and the inputs to the slave flip-flop are Y = 0 and = 1 acts as the S input and R input to the slave, i.e., the S input to the slave is 0 and R input is 1. Therefore, the slave goes to the reset state. The master is not activated when the clock is negative, therefore, even if the input changes there will not be any effect on the final output.

At the instant t1, the clock pulse goes active high and the master is triggered. The inputs to the master are R = 1 and S = 0, therefore, the outputs are Y = 0 and = 1 and the flip-flop goes to the reset state. During this instant the slave is not triggered and it continues to remain in the same state (reset state).

At the instant t2, the clock pulse goes active low and the master is not triggered and remains in the same state (reset state). The slave is triggered and the inputs to the slave are Y = 0 and = 1 making the inputs R = 1 and S = 0. Therefore, the outputs are Q = 0 and = 1 and the flip-flop goes to the reset state.

At the instant t3, the clock pulse goes active high and the master is triggered. The inputs to the master are R = 0 and S = 0, which implies that there is no change in the state of the flip-flop. Therefore, the outputs are Y = 0 and = 1. During this instant the slave is not triggered and it continues to remain in the same state (reset state).

At the instant t4, the clock pulse goes active low and the master is not triggered and remains in the same state (reset state). The slave is triggered and the inputs to the slave are Y = 0 and = 1, making the inputs R = 1 and S = 0. Therefore, the outputs are Q = 0 and = 1 and the flip-flop goes to the reset state.

At the instant t5, the clock pulse goes active high and the master is triggered. The inputs to the master are R = 0 and S = 1; therefore, the outputs are Y = 1 and = 0 and the flip-flop goes to the set state. During this instant the slave is not triggered and it continues to remain in the same state (reset state).

FIGURE 18.13 (a) The master–slave RS flip-flop; and (b) the timing diagram

At the instant t6, the clock pulse goes active low and the master is not triggered and remains in the same state (reset state). The slave is triggered and the inputs to the slave are Y = 1 and = 0 making the inputs R = 0 and S = 1; therefore the outputs are Q = 1 and = 0 and the flip-flop goes to the set state.

It can be observed that between t4 and t5 the S input changes from 0 to 1. However, since the master is not triggered, there will not be any change in the final output. The race-away condition cannot be avoided in the master–slave RS flip-flop since the master is an RS flip-flop.

18.2.9 JK Master–Slave Flip-flops

This uses two JK flip-flops, one as master flip-flop which triggers on the positive pulse of the clock pulse and the other as slave flip-flop which triggers on the negative edge of the clock pulse since the clock input to the slave flip-flop is inverted. Here, one flip-flop (Master) controls another flip-flop (Slave). The master–slave flip-flop using NAND-based JK flip-flops is shown in Fig. 18.14(a).

The output of the master flip-flop changes at the rising edge of the clock (CLK) pulse and the states of Y and are decided by the assignments to J and K. The changes at the output of the master are transmitted to the input of the slave. However, no change can take place at the outputs of the slave (Q and ) until the trailing edge of the clock pulse CLK (rising edge of the ). At the rising edge of the pulse, Q and change and only then the outputs are fed back to the input. As the master and slave circuits are decoupled from one another, the race condition is eliminated in a master–slave JK flip-flop. The Table 18.11 along with the timing diagram, shown in Fig. 18.14(b), explain the working of the JK master-slave flip-flop.

FIGURE 18.14 The JK master-slave flip-flop: (a) using NAND-based SR-latchs; and (b) the timing diagram