18.6 THE PROCEDURE TO DESIGN COUNTERS
The major in the design of counters is briefly described here:
- The statement of the problem or the state diagram will be given.
- Identify the number of flip-flops required.
- Choose the type of flip-flop needed.
- Assign variable names to the flip-flops.
- Draw the state table.
- Develop the excitation table.
- Use a K-map to derive the logic equations.
- Implement a counter to produce the specified sequence of states.
This design procedure can be further understood with the help of the following example.
FIGURE 18.24 A state diagram
Example 18.4: Design a 3-bit binary counter whose state diagram is shown in Fig. 18.25.
FIGURE 18.25 The state diagram of a 3-bit binary counter
Step 1: Since it is a 3-bit counter, the number of flip-flops required is 3.
Step 2: Let the type of the flip-flop be JK flip-flop.
Step 3: Let the three flip-flops be A, B, C
Step 4: The state table is as shown in Table 18.26.
Step 5: The next step is to develop an excitation table from the state table, which is shown in Table 18.27.
Step 6: Now transfer the JK states of the flip-flop inputs from the excitation table to Karnaugh maps (K-maps) given in Tables 18.28(a) – (f) to derive a simplified Boolean expression for each flip-flop input.
TABLE 18.26 The state table
TABLE 18.28 (a) The K-map for JA; (b) the K-map for KA
TABLE 18.28 (c) The K-map for JB; (d) the K-map for KB
From the K-maps, the following expressions for the J and K inputs of each of the flip-flops are obtained:
JC = KC = 1 JB = KB = C JA = KA = B.C
Step 7: The final step is to implement the combinational logic from the equations and connect the flip-flops to form the sequential circuit. The complete logic of a 3-bit binary counter is shown in Fig. 18.26.
FIGURE 18.26 The logic diagram of a 3-bit binary counter