5.2 The Clamping Circuit – Pulse and Digital Circuits

5.2 THE CLAMPING CIRCUIT

The clamping circuit essentially consists of an input source, a capacitor of a suitable value and a diode connected in shunt with the output terminals. This clamps the positive peak of the input signal (sinusoidal, in this case) to the zero level. The diode is assumed to be ideal and initially there is no charge on the condenser. vA is the charge built up on the condenser, C. Figure 5.1 shows a basic clamping circuit.

FIGURE 5.1 A negative clamping circuit

As the input rises from 0 to Vm in the first quarter cycle, D conducts [see Figs 5.2(a) and 5.3(a)], C charges to Vm. During this period, vo = 0 if the diode is ideal. The input falls after the first quarter cycle. vs < Vm, where Vm is the charge on the condenser. As a result, the diode is reverse-biased by a voltage (vsVm). Hence, D is OFF, as shown in Fig. 5.2(b). Thus:

FIGURE 5.2(a) The clamping circuit when the diode is ON

FIGURE 5.2(b) The clamping circuit when the diode is OFF

The voltage across C remains unchanged. From Eq. (5.1) at vs = 0, vo = −Vm. And if, vs = −Vm, vo = −VmVm = −2 Vm and at vs = Vm, vo = vmVm = 0

During the next cycle, the positive peak of the output just reaches the zero level. Hence, in the output, the positive peak is clamped to the zero level. To clamp the positive peak to zero, a negative dc voltage is introduced in this circuit. Therefore, this circuit is called a negative clamp.

Alternatively, if a positive dc voltage is inserted by the clamping circuit so that the negative peak of the input signal is clamped to the zero level, the circuit is called a positive clamp [see Fig. 5.3(b)]. The input to this circuit in Fig. 5.3(b) is a sinusoidal waveform with zero reference level. The output is referenced to +Vm and the negative peak is clamped to zero. The input and output waveforms of negative and positive clamp circuits are represented in Figs. 5.3(a) and 5.3(b), respectively.

FIGURE 5.3(a) The circuit, input and output waveforms of a negative clamp

FIGURE 5.3(b) The circuit, input and output waveforms of a positive clamp

5.2.1 The Clamping Circuit for Varying Input Amplitude

In our description of the clamping circuit in the previous section, a steady input signal was assumed; which is always not the case. The amplitude of the input signal may either increase or decrease for various reasons. So, what is the effect of this variation on the output? To answer this question, let us analyse the behaviour of the circuit under the two possible conditions—increase in amplitude and decrease in amplitude.

If the amplitude of the input increases at t = t1 [see Fig. 5.4(a)], once again the diode D conducts for a quarter cycle. The output is zero for this period. Subsequently, the positive peak of the output remains clamped to zero, as shown in Fig. 5.4(b). Obviously, this simple clamping circuit can clamp the output to zero, even if the input increases. However, the output is distorted for a quarter of a cycle.

FIGURE 5.4(a) The amplitude of the input increases at t1; (b) the output is once again clamped to zero in a quarter cycle

However, this clamping circuit cannot handle an input signal with decreasing amplitude. When the amplitude of the input signal decreases, the voltage across the capacitor should change to the peak amplitude of the new input so as to clamp the positive peak to the zero level. In this circuit, there is no path for the charge on the capacitor to discharge. To facilitate the discharge of the condenser, a resistance R is introduced in shunt with the diode D, as shown in Fig. 5.5(a).

FIGURE 5.5(a) The clamping circuit with a resistance shunted across the diode

It is seen from Figs. 5.5(b)(i) and (b)(ii), at t = t1, if the input amplitude is abruptly reduced, as the voltage across the capacitor cannot change instantaneously, the positive peaks will not reach the zero level. However, as the capacitor discharges, the voltage across the capacitor varies exponentially with a time constant, τ = RC. The output reaches the zero level at t = t2, and the positive peak is again clamped to zero after a few cycles [see Fig. 5.5(b)(iii)]. Let us examine the situation in detail, when the positive peak is clamped to zero as shown in Fig. 5.6.

In the proximity of a positive peak, D conducts and at t = , vo = 0. In the absence of the diode, the output should have followed the dashed line with the peak at t = t2. However, because of the diode, the output is zero from to t2; and in the subsequent cycles the positive peaks of the sinusoidal waveform are clamped to zero. Although, for a small duration between and t2, the output is different from the variation of a sinusoidal signal, i.e., there is a distortion. If the distortion is to be minimized, the capacitor must not lose an appreciable charge in one cycle. For this, the time constant has to be very large as compared to the time period of the input signal.

5.2.2 The Practical Clamping Circuit

In our discussion so far, we have assumed an ideal voltage source with RS = 0. However, a practical voltage source has a finite RS and the influence of RS on the output will have to be taken into account. In this section, we examine the influence of the internal resistance of the voltage source on the output of the clamping circuit. If the internal resistance of the source RS is introduced into the clamping circuit, the modified circuit is as depicted in Fig. 5.7.

FIGURE 5.5(b) (i) The input when the amplitude decreases at t = t1; (ii) the output when R = ∞; and (iii) the output with finite R

When the input is applied to this modified circuit, the output reaches the steady-state value after a few cycles and the positive peaks are clamped to zero. To understand how the output reaches the steady-state, let us examine the equivalent circuits for both the ON and the OFF states of the diode.

When the diode is ON, the circuit is as represented in Fig. 5.8(a). As Rf << R, this circuit reduces to that shown Fig. 5.8(b). For the purpose of computing the output, the circuit in Fig. 5.8(b) may be redrawn as shown in Fig. 5.8(c).

Figure 5.9 (a) depicts the circuit when the diode is OFF. As the reverse resistance Rr >> R, the effective resistance is R and this circuit reduces as shown in Fig. 5.9(b). Again, for computing the output, the circuit in Fig. 5.9(b) is redrawn as in Fig. 5.9(c).

FIGURE 5.6 Output with expanded time scale in the vicinity of a positive peak

FIGURE 5.7 A clamping circuit where RS has been taken into account

FIGURE 5.8(a) The circuit when the diode is ON

FIGURE 5.8(b) The circuit when D is ON and Rf << R

FIGURE 5.8(c) The circuit to calculate the output when the diode is ON

FIGURE 5.9(a) The circuit when D is OFF

FIGURE 5.9(b) The circuit when Rr >> R

FIGURE 5.9(c) The circuit to calculate the output when the diode is OFF

Transient Response. Let us now consider the square wave vs, shown in Fig. 5.10(a), applied as input to the clamping circuit in Fig. 5.7. It is expected that the positive peak of the signal will be clamped to the zero level at the output almost instantaneously, but this does not happen. It takes a few cycles for the positive peak to be clamped to the zero level at the output. When the input is applied, the amplitude of the signal above the zero level goes on decreasing with each successive cycle. The output reaches the steady-state only after a few cycles from the instant the input is applied. The variation of the output with time during this period is called the transient response. At the end of this period when the positive peak is clamped to the zero level, the output is said to have reached the steady state.

We now examine how the output reaches the steady-state value after a few cycles (transient response). The variation of the output for the first few cycles, during the periods when the diode is ON and OFF, is then calculated. The input to the clamping circuit is a square wave with a peak-to-peak amplitude V and a finite frequency f (= 1/T) as shown in Fig. 5.10(a).

At t = 0+, the diode is ON. Using the equivalent circuit shown in Fig. 5.8(c):

If RS = Rf:      vo(0+) =

FIGURE 5.10(a) The input and output waveforms of the clamping circuit

FIGURE 5.10(b) The equivalent circuit to compute the output when D is OFF

During the period 0 to T/2, as the input remains constant, the output decays exponentially with the time constant τ = C(RS + Rf); and at t = T/2; the voltage across Rf is:

Hence, the total voltage across (Rs + Rf) = 2vo (T/2). The voltage across C is [V − 2vo (T/2)].

Now at t = T/2, the input falls to 0 V, and the diode is OFF. The equivalent circuit shown in Fig. 5.10(b) is the same as the equivalent circuit shown in Fig. 5.9(c), except that the capacitor voltage is indicated here. Since RS << R, the output voltage vo is almost the same as [V − 2vo (T/2)] but with a negative sign. Hence the output at (T/2)+ abruptly falls to [V − 2vo (T/2)]. During the period T/2 to T, the input remains constant, the output decays exponentially with the time constant τ = C(R + Rs).

The input once again changes by V. The process is repeated over a few cycles till a steady-state value is reached. Example 5.1 elucidates the process.

EXAMPLE

Example 5.1: The input in Fig. 5.11(a) is applied to the practical clamping circuit in Fig. 5.11(b). Compute the output till it reaches the steady-state. Given that f = 5 kHz, Rs = 0.1 kΩ, Rf = 0.1 kΩ, Rr = ∞.

FIGURE 5.11(a) The Input, (b) the given practical clamping circuit

Solution: Assume that initially the capacitor is uncharged. The input to the circuit is a symmetric square wave whose amplitude varies from −20 V to 20 V. When the diode is conducting, using the circuit shown in Fig. 5.8(c), the output voltage can be calculated. Using Fig. 5.11(c):

FIGURE 5.11(c) The circuit to calculate the output when D is ON

When the input abruptly changes by 20 V, the output also jumps by 10 V. As the input is constant during the period 0 to T/2, the output decays exponentially with time constant τ.

 

τ = (Rf + RS)C = 0.2 × 103 × 1 × 10−6 = 0.2 ms

As

f = 5 kHz,     T = = 0.2 ms     T/2 = 0.1 ms, T = τ

Hence,

Using Fig. 5.11(d), we can calculate the voltage vA across C. The voltage across capacitor vA is:

 

vA = 20 V − (6 V + 6 V) = 8 V

FIGURE 5.11(d) Circuit to calculate vA

At t = T/2, the input falls to −20 V, the diode is in the OFF state and the equivalent circuit of Fig. 5.11(e) is used. As R >> RS, the drop across RS is negligible. This circuit is redrawn as shown in Fig. 5.11(f).

 

vo = −20 V − 8 V = −28 V

The output falls to −28 V suddenly. As the input remains constant from T/2 to T, the output decays with time constant τ = 10.1 kΩ × 1μF = 10.1 ms. Thus, T/2 is 0.1 ms and τ = 10.1 ms, which implies that T/2 << τ. Hence, there is no appreciable decay of the output when,

 

vo(T) = −28 eT/τ ≈ −28 V

FIGURE 5.11(e) Circuit to calculate the output when D is OFF

In other words, the output remains constant. In the interval T/2 to T, as the output remains constant, the voltage across the capacitor remains unchanged. At t = T, the input abruptly rises to 20 V. At that instant, D is ON, as the voltage across C is 8 V, vo = 6 V and in the interval T to 3T/2 the output voltage decays exponentially.

Voltage across C = vA = 20 − (3.6 + 3.6) = 12.8 V and at t = 3T/2, vo = −20 V − 12.8 V = −32.8 V

As the voltage does not change much during the interval 3T/2 to 2T, at t = 2T, the output again returns to 3.6 V.

 

At t = 5T/2

 

vo = 3.6 e−1/2 = 2.2 V

vA = 20 − (2.2 + 2.2) = 15.6 V

vo = −20 V − 15.6 V = −35.6 V

The output remains at −35.6 V during the interval 5T/2 to 3T. This again returns to 2.2 V at t = 3T and decays during the interval 3T to 7T/2.

FIGURE 5.11(f) The simplified circuit to calculate the output voltage vo

FIGURE 5.12(a) The given waveforms; (b) the output waveforms

= 2.2 e−1/2 = 1.33 V        vA = 20 − (1.33 + 1.33) = 20 − 2.66 = 17.34 V

vo = −20 V − 17.34 V = −37.34 V

This procedure is repeated. It is seen that the output reaches the steady state in a few cycles, wherein the positive peaks of the input are clamped to a zero level (strictly speaking, to Vγ) at the output (see Fig. 5.12).

Calculating the Steady-state Voltages. It is seen from Example 5.1 that if a square wave is applied as an input to a clamping circuit, the output reaches the steady-state value after a few cycles. Hence, for the input in Fig. 5.13(a), the output of the clamping circuit is given in 5.13(b).

The output at the steady-state is as shown in Fig. 5.13(b) with voltage levels V1, , V2 and ; these can be plotted to scale after calculation. To calculate these four unknowns, four equations to be are obtained:

Consider the situation at t = 0−

At

t = 0−, vs = V and vo =

The diode is reverse-biased and the corresponding equivalent circuit is as shown in Fig. 5.14(a).

The voltage across the capacitor terminals at t = 0− is:

FIGURE 5.13(a) The input to the clamping circuit; and (b) the steady-state output

Substituting the values of vs and vi in Eq. (5.2):

Consider the situation at the instant t = 0+. At t = 0+, vs = V and vo = V1. The diode is ON and the corresponding equivalent circuit is as shown in Fig. 5.14(b).

FIGURE 5.14(a) The equivalent circuit when the diode is reverse-biased

FIGURE 5.14(b) The equivalent circuit when the diode is forward-biased

The voltage across the capacitor terminals at t = 0+ is:

Since the voltage across the capacitor cannot change instantaneously

vA(0−) = vA(0+).

Hence, from Eqs. (5.3) and (5.4):

The peak-to-peak amplitude of the input is V. Therefore,

 

V = VV

From Eq. (5.5):

Once again consider the situation at t = T1−, when vs = V and vo = and the diode is ON. The equivalent circuit is shown in Fig. 5.14(c).

Similarly, at t = T1+, since D is OFF, from the equivalent circuit shown in Fig. 5.14(d):

Again, as vA(T1−) = vA(T1+), from Eqs. (5.7) and (5.8):

Further at t = 0+, vo = V1 and in the interval 0 to T1, vo decays with a time constant (Rf + Rs) C. Hence:

Similarly, in the interval T1 to T2, the diode is reverse-biased and the circuit time constant is (Rs + R) C. The voltage V2 decays to .

Equations (5.6), (5.9), (5.10) and (5.11) will enable us to determine the voltages V1, , V2 and . If in the circuit shown in Fig. 5.7 Rs = 0, equations (5.6) and (5.9) reduce to:

FIGURE 5.14(c) The circuit to calculate vA(T1−)

FIGURE 5.14(d) Circuit to calculate vA (T1+)

It is evident from the above discussion that the output is independent of the levels V and V associated with the input and is only determined by the amplitude V.

Subtracting Eq. (5.9) from Eq. (5.6):

If V1 = Δf and V2 = Δr, from Eq. (5.13):

If Rs << R

where, Δf is the tilt in the forward direction and Δr is the tilt in the reverse direction.

If Rs << Rf:

5.2.3 Clamping the Output to a Reference Voltage (VR)

In the clamping circuit seen in Fig. 5.7, the positive peak of the input signal is clamped to the zero level at the output. However, if the positive peak is to be clamped to a chosen reference voltage VR for the circuit in Fig. 5.7, a dc voltage VR is to be included in the output. The circuit in Fig. 5.15 shows a clamping circuit similar to that seen in Fig. 5.7 except for the fact that a reference voltage VR is included and Rs is zero.

To obtain the steady-state response of the circuit, we assume that VR is zero. This circuit, then, is the clamping circuit that clamps the positive peak of the input signal to Vγ as shown in Fig. 5.7.

The steady-state responses for symmetric and unsymmetric square-wave inputs are plotted in Fig. 5.16(a) and Fig. 5.16(b), respectively.

Solving the four equations [Eqs. (5.6), (5.9), (5.10) and (5.11)], the values of V1, , V2 and can be evaluated. To find these steady state output voltages with VR included, add the value of VR to each of these values. If, on the other hand, the polarity of VR is reversed, add −VR to each of the values computed. The result is that the positive peak in the output is clamped to −VR, as shown in Fig. 5.17.

FIGURE 5.15 The circuit that clamps the positive peak of the input to VR

FIGURE 5.16 The steady-state response for (a) symmetric square-wave input; and (b) unsymmetric square-wave input

FIGURE 5.17 The positive peak of the input clamped to -VR

FIGURE 5.18 (a) The negative peak of the input clamped to +VR; and (b) the negative peak of the input clamped to −VR

Similarly, look at the circuits in Fig. 5.18(a) and (b). The circuits here clamp the negative peak of the input to +VR and −VR respectively. To simplify the analysis of the clamping circuits let us assume:

  1. The forward resistance of the diode D when ON is negligible. We assume that there is no distortion in the output when D is ON.
  2. The time constant τ (= RC) is so large when compared to the time period of the signal under consideration that practically there is no change in the voltage on the condenser C, when D is OFF.
  3. The internal resistance of the source vs, RS = 0.

Based on these assumptions, a simple and straight forward method to analyse clamping circuits is as follows:

 

Step 1: Start the analysis from the time duration during which D is ON. If the starting time duration keeps D OFF, skip that time interval.

Step 2: Consider the relevant circuit, taking care of the polarities of the voltages. Calculate vo.

Step 3: Find vA, the voltage on C.

Step 4: Consider the next time interval. Draw the circuit, taking care of the polarities of the input and vA. Calculate vo.

If the input is periodic you can plot the steady-state output. To understand the procedure let us consider an example.

EXAMPLE

Example 5.2: For the clamping circuit shown in Fig. 5.19(a) from the given input, calculate and plot the steady-state output. Given C = 0.1 μF, R = 100 kΩ, VR = 5 V, f = 5000 Hz.

FIGURE 5.19(a) The given biased clamping circuit with input and output waveforms

Solution: Given f = 5000 Hz. Therefore, T = = 0.2 ms.

= 0.1 ms, τ = RC = 100 × 103 × 0.1 × 10−6 = 10 ms.

τ >> T/2, hence the voltage on C remains unchanged during the period D is OFF.

 

Step 1: During the interval 0 to 0.1ms, as vs is -10 V D is OFF and vo = 0.

Step 2: During the interval 0.1 to 0.2 ms, vs is 20 V, hence D is ON. The circuit of Fig. 5.19(a) is drawn as shown in Fig. 5.19(b), vo = 5 V

Step 3: Now applying the KVL equation around the input loop, we have: vA = vsVR = 20−5 = 15 V. The assumption is that vA remains unchanged.

Step 4: During 0.2 to 0.3 ms, D is OFF. vA = 15 V, vs = −10 V. The circuit is as shown in Fig. 5.19(c).
Thus: vo = −vsvA = −10 − 15 = −25 V.

The output waveform is plotted in Fig. 5.19(a). The positive peak of the input is clamped to +5 V. The peak-to-peak swing at the input is 30 V. It remains the same in the output.

FIGURE 5.19(b) The circuit when D is ON during 0.1 to 0.2 ms

FIGURE 5.19(c) The circuit during 0.2 and 0.3 ms when D is OFF

EXAMPLE

Example 5.3: Working with the same circuit and inputs, repeat Example 5.2, using a Si diode with VAK = 0.7 V, when D is ON.

Solution:

 

Step 1: During the interval 0 to 0.1ms, as vs is −10 V, D is OFF and vo = 0.

Step 2: During the interval 0.1 to 0.2 ms, vs is 20 V, hence D is ON. The circuit of Fig. 5.19(a) is drawn as shown in Fig. 5.19(d). vo = 5.7 V

Step 3: Now applying the KVL equation around the input loop, we have:

 

vA = vsVRVAK = 20 − 5 − 0.7 = 14.3 V

Step 4: During 0.2 to 0.3 ms, D is OFF, vA = 14.3 V, vs = −10 V. The circuit is shown in Fig. 5.19(e). Thus:

 

vo = −vsvA = −10 − 14.3 = −24.3 V.

FIGURE 5.19(d) Circuit when D is ON during 0.1 to 0.2 ms

The output waveform is plotted in Fig. 5.19(f). The positive peak of the input is clamped to +5.7 V. The peak-to-peak swing at the input is 30 V. It remains the same in the output also.

FIGURE 5.19(e) The circuit during 0.2 and 0.3 ms when D is OFF

FIGURE 5.19(f) The output waveform

EXAMPLE

Example 5.4: Draw the steady-state output waveform for the given biased clamping circuit shown in Fig. 5.20, when the input is a square-wave signal of amplitude ±10 V. Assume that C is large.

FIGURE 5.20 The given biased negative clamper with VR = −5 V

Solution: The diode D conducts, when the input changes to +10 V, Vo = −5 V Then the capacitor charges to (vsvo) = 15 V.

Under steady-state conditions vo = vsvA = vs − 15 V

When vs = 10 V, vo = 10 − 15 = −5 V

When vs = −10 V, vo = −10 − 15 = −25 V

The positive peak is clamped to VR = −5 V, in the output, as shown in Fig. 5.20.

EXAMPLE

Example 5.5: Draw the steady-state output waveform for the given biased clamping circuit shown in Fig. 5.21, when the input is ± 10 V square wave. Assume that C is large.

FIGURE 5.21 The given biased positive clamper with VR = 5 V

Solution: The diode D conducts, when vs changes to −10 V, then the capacitor charges to vA = −15 V.

Under steady-state conditions vo = vs − (−vA) = vs + vA = vs + 15 V

When vs = 10 V, vo = 10 + 15 = 25 V

When vs = −10 V, vo = −10 + 15 = 5 V

The negative peak is clamped to VR = 5 V in the output, Fig. 5.21.

EXAMPLE

Example 5.6: Draw the steady state output waveform for the given biased clamping circuit shown in Fig. 5.22, when the input is ± 10 V square wave. Assume that C is large.

FIGURE 5.22 The given biased positive clamper with VR = −5 V

Solution: The diode D conducts, when vs changes to −10 V. Then the capacitor charges to vA = vSVR = −10 − (−VR) = −5 V.

Under steady-state conditions, vo = vs − (−vA) = vs + vA = vs + 5 V.

When vs = 10 V, vo = 10 + 5 = 15 V.

When vs = −10 V, vo = −10 + 5 = −5 V.

The negative peak is clamped to VR = −5 V in the output, as shown in Fig. 5.22.

5.2.4 The Design of a Clamping Circuit

Let us now try to design a clamping circuit to clamp the positive peak of an input signal (say, a sinusoidal signal) to zero level as shown in Fig. 5.5(a). As discussed in Section 5.2.1 earlier, when the diode is OFF, ideally its reverse resistance is either infinity or, in practice, very large (of the order of tens of mega ohms). If the input abruptly falls in amplitude, as shown in Fig. 5.5(b), the time constant associated with the discharge of C(= RrC) is large. Then the positive peak of the signal in the output may not be clamped to zero, even after many cycles, in the absence of R. In numerous applications, the requirement is that the signal should once again be clamped to zero level in at least a few cycles. Hence, R is shunted across the diode D to reduce the time constant. On this account, R is so chosen that it is significantly smaller than Rr Hence,

where a is a large number. During the period the diode is OFF, some charge is lost by the condenser C. This lost charge is replenished when the diode is ON; during this period the resistance offered by the diode is Rf, which is very small (of the order of few tens of ohms). To ensure that the charge is acquired by the capacitor in a relatively small amount of time, R should be significantly larger than Rf. Hence,

From Eqs. (5.17a) and (5.17b),

If the relation between f (= 1/T), the frequency of the applied input and RC is specified as a desired value k:

Then C is chosen as:

If the negative peak of the input is to be clamped to VR1 as in Fig. 5.23, the reference voltage to be assigned is

where VD is the diode voltage when ON. Let us consider a specific example to illustrate this.

EXAMPLE

Example 5.7: Design a clamping circuit to clamp the negative peaks to 5 V given that Rf = 0.1 kΩ, Rr = 1000 kΩ, VR1 = 5 V, f = 2 kHz and k = 10, VD = 0.7 V.

Solution: Using Eq. (5.17a):

FIGURE 5.23 The given biased positive clamping circuit and the steady-state output

Using Eq. (5.19):

As the negative peak is required to be clamped to +5 V, the reference voltage source is chosen using Eq. (5.20) as:

 

VR = VR1 + VD = 5 + 0.7 = 5.7 V

The circuit with input and output waveforms is shown in Fig. 5.23.