# 5.3 The Effect of Diode Characteristics on the Clamping Voltage – Pulse and Digital Circuits

##### 5.3 THE EFFECT OF DIODE CHARACTERISTICS ON THE CLAMPING VOLTAGE

For the clamping circuit shown in Fig. 5.7, to obtain the steady-state response, the diode is replaced by Rf when ON and Rr = ∞ when OFF. Though the positive peak of the signal in the output is ideally required to be clamped to the zero level, in practice it is clamped to a voltage Vcl = Vγ, where Vγ is the cut-in voltage of the diode. In a practical diode, the current variation is non-linear in nature. Hence, we consider the influence of the diode characteristics on the clamping voltage, Vcl and show that the clamping voltage (Vcl) changes with a change in the amplitude of the input signal. Let us consider the clamping circuit described in Fig. 5.7 and let its input be a symmetric square wave as shown in Fig. 5.24(a). FIGURE 5.24(a) A symmetric square-wave input with peak-to-peak amplitude V

If C is large, irrespective of whether the diode is ON or OFF, the time constants are large so that the output is also a square wave. The steady-state output has a general form as shown in Fig. 5.24(b). FIGURE 5.24(b) The steady-state output with a large C

In obtaining the steady-state response, we assumed that the diode is ideal with a small Rf. In practice, however, an idealized diode, when ON, is represented as a switch in series with a battery voltage of Vγ, a resistance Rf [see Figure 5.24(c)]; and biased by V as shown in Fig. 5.24(a).

We now consider the V–I characteristic of the practical diode to understand the influence of the diode characteristics on the clamping voltage. The diode current is given by the relation: When the diode is ON, the positive peak of the signal is clamped to Vcl and the current in the diode is Icl. Vcl is the voltage to which the positive peak is clamped.  FIGURE 5.24(c) The equivalent circuit of the forward-biased diode

The equivalent circuit when the diode is ON, when vs = V with RS = 0 is shown in Fig. 5.24(d). From Fig. 5.24(d): During the negative half-cycle of the square-wave input, vs = V and the diode is OFF. The equivalent circuit is given in Fig. 5.24(e).

From Fig. 5.24(e): And Using Eqs. (5.24) and (5.25): In practice, VclVγ and V can be typically of the order of a few tens of volts. Thus, V >> Vcl. From Eq. (5.26):  FIGURE 5.24(d) The equivalent circuit when the diode is ON FIGURE 5.24(e) The equivalent circuit when the diode is OFF

As the net voltage across R is V, Ir the discharging current of C is given by the relation: As the input is a symmetric square wave, under steady-state, the charge gained by C when the diode is ON should be equal to the charge lost by C when the diode is OFF.

Therefore, From Eqs. (5.22) and (5.28): Taking logarithms to the natural base:  Equation (5.31) gives the steady-state clamping voltage and Eq. (5.32) describes the variation in the clamping voltage with a change in the amplitude of the input signal. For a silicon diode used in a clamping circuit for which Vcl = Vγ = 0.5 V, η =2, V = 10 V and dV = 1 V: Equation (5.32) suggests that as V increases, the change in the clamping voltage, dVcl, becomes smaller. Also, when the diode is ON, V is the forward-bias. Hence, to ensure that the clamping voltage remains unaltered, the diode must be forward-biased by a larger voltage. The circuit for this is represented in Fig. 5.25(a).

Let us now try to calculate dVcl for this circuit to verify whether this arrangement really ensures negligible change in Vcl or not. Redrawing the circuit in Fig. 5.25(a) gives Fig. 5.25(b). The equivalent circuit when the diode is ON, i.e., when vs = V, is shown in Fig. 5.25(c). FIGURE 5.25(a) A clamping circuit in which the diode is forward-biased by a large voltage VYY FIGURE 5.25(b) The modified circuit of Fig. 5.25(a)

From Eq. (5.22):

Icl = I0eVcl/ηVT

From Fig. 5.25(c): as Vcl << VYY.

Writing the KCL equation at node A:  Also, When the input goes to V, the diode is OFF and the equivalent circuit is as shown in Fig. 5.25(d).

The discharging current Ir is: FIGURE 5.25(c) The equivalent circuit of Fig. 5.25(b) when the diode is forward-biased FIGURE 5.25(d) The equivalent circuit of Fig. 5.25(b) when the diode is OFF since R >> RS. Put Eq. (5.36) in (5.37): But VV = V. Therefore: We know that V >> Vcl and RS << R. Therefore: As the input is a symmetric square wave, If = Ir. Therefore, from Eqs. (5.35) and (5.38): As RS << R: From Eq. (5.22): Taking logarithms to the natural base:  If a Si diode used in the clamping circuit, for which η = 2, VT = 26 mV, dV = 1 V, V = 10 V and VYY = 50 V: On the contrary, dVcl (when VYY = 0) = 5.2 mV (calculated earlier).

We see from the above calculations that dVcl with large VYY (= 50 V) is approximately one-tenth of dVcl with VYY = 0. Thus, the use of a biased diode improves the stability of the clamping level. However, one major constraint in the circuit of Fig. 5.25(a) is that the diode will remain ON continuously if the input signal (V) is small. The minimum peak-to-peak value of the signal V can be determined as follows:

When the input magnitude is V, D is ON, the voltage across the diode is Vγ so that the current in R is [from Eq. (5.33)]: When the input drops by V, the current IS through RS is, IS = −V/RS. If IR >> IS, then the diode is continuously ON. Therefore, to make sure that diode switches OFF when the input falls to V, IRIS. Hence, for the proper circuit operation, Eq. (5.42) has to be satisfied in the clamping circuit of Fig. 5.25(a).