5.4 Synchronized Clamping – Pulse and Digital Circuits

5.4 SYNCHRONIZED CLAMPING

In the clamping circuits examined in this chapter, the duration for which clamping is effective is controlled by the signal alone—the signal remains clamped as long as its amplitude remains unaltered. However, in some applications it may become necessary that the time of clamping be determined by the control or gating signal that occurs synchronously with the signal. Two or more signals are said to be synchronized if they arrive at a particular reference point in their cycles at the same time. The simultaneous presence of the gating signal during the period of constant amplitude input enables the two waveforms to be synchronized and the output to be referenced to VR. One typical application could be in a CRO, where, for the spot to move vertically, the signal applied to the X-deflecting plates of the CRT varies in both directions but returns to a reference level VR, as shown in Fig. 5.26(a).

FIGURE 5.26(a) The signal that varies in both directions but is referenced to VR

Let the signal then be transmitted through a capacitive coupled network like a high-pass network shown in Fig. 5.26(b).

For the duration 0 to T1, when the input is a ramp, the output varies exponentially from point A with a time constant τ. At t = T1, both the input and the output fall by V, giving rise to an undershoot. During the interval T1 to T2, as the input remains constant, the output decays exponentially to zero (point B). A similar variation takes place during the period the signal is negative. The resultant output waveform vo is shown in Fig. 5.26(c).

FIGURE 5.26(b) A high-pass RC circuit

FIGURE 5.26(c) The output of a capacitive coupling network (high-pass circuit)

This output is devoid of a dc component. To reintroduce the dc component, we apply a signal referenced to the zero level [see Fig. 5.27(a)] as input to the circuit, as shown in Fig. 5.27(b). The output waveform of this circuit is shown in Fig. 5.28.

FIGURE 5.27(a) The input signal;

(b) The switch S operates in sync with the signal to clamp the output to VR

FIGURE 5.28 The output of the circuit in Fig. 5.27(b)

FIGURE 5.29(a) A synchronized clamping circuit

When the switch S closes, during the interval T2, vo = VR. When the switch S opens during the interval T1, C charges resulting in the waveform shown in Fig. 5.28. The small spikes can be reduced to negligible values if the switch has a zero resistance in the ON position.

The circuit in Fig. 5.27(b) can be implemented practically using diodes D1 and D2, and two control signals v1 and v2, with a 180° phase shift, as shown in Figs. 5.29(a), 5.30(a) and 5.30(b). If the signal in Fig. 5.30(c) is referenced to the zero level; the output in Fig. 5.30(d) is referenced to VR.

FIGURE 5.29(b) The circuit when D1 and D2 are ON; and (c) the circuit when D1 and D2 are OFF

FIGURE 5.30 The waveforms of a synchronized clamping circuit

Tc is the time duration of the control signals and Tn is the time period during which the control signals are zero. The input to the clamping circuit is synchronized with the control signals v1 and v2. Since the input vs is referenced to the zero level, the purpose of this circuit is to introduce a dc voltage (VR) so that the output vo is now referenced to VR instead of the zero level. From the circuit in Fig. 5.29(a), it is evident, for the given polarities of the control signals that the diodes D1 and D2 conduct during the period Tc, resulting in the circuit of Fig. 5.29(b). As v1 and v2 are of equal magnitudes but of the opposite polarity, their net effect is zero at the output. The result is the output VR.

However, when the control signals are zero, diodes D1 and D2 are OFF, resulting in the circuit of Fig. 5.29(c). The input is transmitted to the output terminals with a slight distortion in amplitude, as the capacitor charges exponentially. The output of this circuit is now referenced to VR, meaning that a dc voltage VR is introduced by the clamping circuit.