5.5 The Clamping Circuit Theorem – Pulse and Digital Circuits

5.5 THE CLAMPING CIRCUIT THEOREM

This theorem enables us to calculate the voltage level to which the output is clamped by considering the areas above and below the reference level, when the values of Rf and R are known.

The clamping circuit theorem states that under steady-state conditions, for any input waveform, the ratio of the area under the output voltage curve in the forward direction to that in the reverse direction is equal to the ratio Rf/R. To prove the clamping circuit theorem, consider a typical steady-state output for the clamping circuit, represented in Fig. 5.31.

In the time interval t1 to t2, D is ON. Hence, during this period, the charge builds up on the capacitor C. If if is the diode current, the charge gained by the capacitor during the interval t1 to t2 is:

However, if = Vf/Rf, where Vf is the diode forward voltage:

During the interval t2 to t3, D is OFF. Hence, the capacitor discharges and the charge lost by C is:

FIGURE 5.31 Typical steady-state output of the clamping circuit

Put ir = Vr/R, where Vr is the diode reverse voltage:

At steady state, the charge gained is equal to the charge lost. In other words, q1 = q2.

Therefore,

However,

FIGURE 5.32 The output of the clamping circuit when C is large

Here, Af is the area with D in the ON state and Ar is the area under the output curve with D in the OFF state.

From Eqs. (5.47) and (5.48):

This relation is known as the clamping circuit theorem.

Consider Fig. 5.32 in which the output of the clamping circuit is assumed to remain almost constant during the periods T1 and T2 when the diode D is ON and OFF by choosing large values of C.

If V1 and T1 are the voltage and time duration above the reference level and V2 and T2 are the voltage and time duration below the reference level under steady-state, then as per this theorem:

Assuming that T1, T2, Rf, R and the amplitude of the signal V are known, it is possible to compute the voltage level V1 to which the signal is clamped at the output.

SOLVED PROBLEMS

Example 5.8: The input shown in Fig. 5.33(a) is applied to the clamping circuit [see Fig. 5.33(b)]. Plot the output waveform. Given that Rs = Rf = 50 Ω, R = 10 kΩ, Rr = ∞, C = 1μF

FIGURE 5.33(a) The given Input; and (b) the given clamping circuit

Solution: The equivalent circuit, when the diode conducts, is shown in Fig. 5.34(a). When the diode does not conduct, the equivalent circuit is as shown in Fig. 5.34(b).

FIGURE 5.34(a) The equivalent circuit when D is ON

FIGURE 5.34(b) The equivalent circuit when D is OFF

  1. At t = 0.1 ms, vs abruptly rises to 8 V. As the capacitor cannot allow sudden changes in the voltage it behaves as a short circuit.
  2. The input remains constant at 8 V from 0.1 to 0.2 ms. So vo decays exponentially with time constant (Rs + Rf) C.

    At t = 0.2 ms

    vo = 4 e−0.1×10−3/(50+50)(1×10−6) = 4e−1 = 1.47152 V

    Voltage across the capacitor = vA = 8 − 2 × 1.47152 = 5.05696 V

  3. At t = 0.2 ms, vs abruptly falls to −5 V. The resultant circuit is as shown in Fig. 5.34(c).

     

    vo = −5 − 5.05696 = −10.05696 V

  4. From t = 0.2 ms to 0.3 ms, vs remains at −5 V. Hence, the output voltage should decay exponentially with a time constant (R + Rs) C.

    At 0.3 ms,

    vo = −10.05696 e−0.1×10−3/(10000+50)(1×10−6) = −9.958 V

    Voltage across C = vA = −5 + 9.958 = 4.958 V

  5. At t = 0.3 ms and vs = 5 V. The equivalent circuit to be considered is shown in Fig. 5.34(d).

FIGURE 5.34(c) The circuit to calculate the output

As vs remains constant, vo decays exponentially from t = 0.3 ms to 0.4 ms.

At t = 0.4 ms vo = 0.0213 e−1 ≈ 0 V. The output voltage now varies as shown in Fig. 5.34(e).

FIGURE 5.34(d) The circuit to calculate the output

FIGURE 5.34(e) The steady-state output waveform

Example 5.9: A clamping circuit and the input applied to it are shown in Fig. 5.35(a) and (b). Calculate and plot to scale the steady-state output. Given that: Rs = Rf = 100 Ω, T1 = T2 = 500 μs.

Solution: To calculate the steady-state voltages, first calculate V1, , V2 and by making VR = 0. During the interval 0 to T1, the charging time constant of the capacitor C is:

 

τf = (Rs + Rf) C = (100 + 100)0.5 × 10−6 = 100 μs

The capacitor discharges during the interval T1 to T2 and the time constant, τr, is:

 

τr = (Rs + R)C = (100 + 200000)0.5 × 10−6 = 100050 μs = 100.050 ms

FIGURE 5.35(a) The given input; and (b) clamping circuit

FIGURE 5.35(c) The steady-state output

Also,

Solving Eqs. (1), (2), (3) and (4):

 

V1 = 0.2516 V,         = 0.0017 V        V2 = −99.996 V         = −99.496 V

To get the steady-state output, we add VR to the values of V1, , V2 and for the given circuit in Fig. 5.35(a). Therefore,

 

V1 = 5.2516 V         = 5.0017 V        V2 = −94.996 V         = −94.496 V.

The steady-state output is as shown in Fig. 5.35(c).

Example 5.10: Draw the output waveform under the steady state for the given biased clamping circuit shown in Fig. 5.36, when the input is 10 V square wave. Assume that C is very large so that the change in the output voltages during the periods when D is ON and OFF is negligible.

FIGURE 5.36 The given biased negative clamper with VR = 5 V and the corresponding input and output waveforms

Solution: The diode D conducts when the input changes to +10 V. Then capacitor charges to +5 V after few cycles.

Under steady-state conditions vo = vsvA = vs − 5

When vs = 10 V, vo = 10 − 5 = 5 V

When vs = −10 V, vo = −10 − 5 = −15 V

The positive peak is clamped to VR(= 5V), in the output.

SUMMARY
  • The dc component, that is blocked when a signal passes through a capacitive coupling network can again be restored using a clamping circuit.
  • A clamping circuit, generally, is called a dc restorer and dc re-inserter, meaning that it reintroduces exactly the same amount of dc voltage lost. However, it is a dc inserter, which means that it introduces any desired dc voltage.
  • A simple clamping circuit consists of a signal source, a capacitor of appropriate value and a diode connected across the output terminals.
  • The positive or negative extremity of an input signal can be clamped to a zero level or to an arbitrarily chosen reference level by using a clamping circuit.
  • The dc level associated with the input signal has absolutely no say in determining the steady-state response of the clamping circuit.
  • The clamping circuit theorem states that for any input waveform under steady-state conditions Af/Ar = Rf/R.
  • A synchronized clamping circuit is one in which the time of clamping is not determined by the signal but by a control signal which is in synchronization with the signal.
MULTIPLE CHOICE QUESTIONS
  1. Strictly speaking, a clamping circuit should be called:
    1. dc restorer
    2. dc reinserter
    3. dc eliminator
    4. dc inserter
  2. A positive clamping circuit is one that clamps:
    1. The positive extremity of the signal to the zero level
    2. The positive extremity of the signal to a positive dc voltage
    3. The negative extremity of the signal to the zero level
    4. None of the above
  3. A negative clamping circuit is one that clamps:
    1. The positive extremity of the signal to the zero level
    2. The positive extremity of the signal to a positive dc voltage
    3. The negative extremity of the signal to the zero level
    4. None of the above
  4. The clamping theorem states that:
  5. In a clamping circuit, the tilts in the forward and reverse directions are related by:
    1. None of the above
SHORT ANSWER QUESTIONS
  1. What is a clamping circuit?
  2. Why do we call a clamping circuit a dc inserter?
  3. What do you understand by positive clamping and negative clamping?
  4. State the clamping circuit theorem.
  5. What is synchronized clamping?
  6. If , show that Δf = Δr when RS is small
  7. What do you understand by biased clamping?
LONG ANSWER QUESTIONS
  1. A sinusoidal signal is applied as an input to a negative clamping circuit and suddenly the amplitude of the input signal falls. Explain how clamping is restored in the circuit?
  2. State and prove the clamping circuit theorem.
  3. Consider the steady-state output waveform of a clamping circuit for a square-wave input and derive the relation between the tilt in the forward direction to that in the reverse direction.
  4. Explain the principle of synchronized clamping.
  5. Discuss the influence of the diode characteristics on the clamping voltage.
UNSOLVED PROBLEMS
  1. Design a diode clamper shown in Fig. 5p.1 to restore the positive peaks of the input signal to a voltage level to 5 V. Assume the diode cut-in voltage is 0.5 V, f = 1 kHz, Rf = 1 kΩ, Rr = 200 kΩ and RC = 20 T.

    FIGURE 5p.1 The given clamping circuit with reference voltage VR

  2. For the excitation as shown in Fig. 5p.2(a) and the clamping circuit [see Fig. 5p.2(b)], calculate and plot to scale, the steady-state output.

    FIGURE 5p.2 The given Input, and (b) the clamping circuit

  3. Sketch the steady-state output voltage for the clamper circuit shown in Fig. 5p.3 and locate the output dc level and the zero level. The diode used has Rf = 100 Ω, Rr = 500 kΩ, Vγ = 0.C is arbitrarily large and R = 20 kΩ. The input is a ±20V square wave with 50 per cent duty cycle.

    FIGURE 5p.3 The given clamping circuit for problem 2

  4. For the circuit shown in Fig. 5p.4(a), Rs = Rf = 50 Ω, R = 10 kΩ, Rr = ∞, C = 2.0 μF, the input varies as shown in Fig. 5p.4(b). Plot the output waveform.

    FIGURE 5p.4 The given input; and (b) the given clamping circuit

  5. The input as shown in Fig. 5p.5(a) is applied to the clamping circuit shown in Fig. 5p.5(b) with Rs = Rf = 100 Ω, R = 10 kΩ, Rr = ∞, C = 1.0 μF; Vγ = 0. Draw the output waveform and label all the voltages.

    FIGURE 5p.5 The given input; and (b) the given clamping circuit

  6. A clamping circuit and input applied to it are shown in Fig. 5p.6. Assume that C is quite large. Find at which voltage level the positive peak is clamped in the output if T1 = 1 ms, T2 = 1μs, Rf = 100 Ω and R = 100 kΩ.

    FIGURE 5p.6 The given input and clamping circuit for problem 3

    (Hint: Use the clamping Theorem.)

  7. Calculate and draw the steady-state output waveform of the circuit in Fig. 5p.7. Assume Rf = 50 Ω, Rr = 500 kΩ and T1 = T2 = 1 ms.

    FIGURE 5p.7 The given clamping circuit with large

  8. Design a biased clamping circuit to derive the output voltage as shown in Fig. 5p.8(b), given the input as shown in Fig. 5p.8: (a) f = 1000 Hz, Rf = 100 Ω, Rr = 1MΩ and RC/T = 10. Assume that D is ideal.

    FIGURE 5p.8 (a) The given input to the clamping circuit; and (b) the required output