# 8.2 Collector-coupled Monostable Multivibrators – Pulse and Digital Circuits

##### 8.2 COLLECTOR-COUPLED MONOSTABLE MULTIVIBRATORS

The collector-coupled monostable multivibrator is shown in Fig. 8.1. When compared to an astable multivibrator as shown in Fig. 7.1, it is evident that the output from the second collector to the first base is through a resistance R1. Hence, this circuit has one stable state and one quasi-stable state.

As a negative voltage is connected to the base of the first device, it is possible that Q1 may be OFF. In the stable state, let Q1 be OFF and Q2 be ON and in saturation. Therefore:

VC1 = VCC    VC2 = VCE(sat)    VB2 = VBE(sat) = Vσ

The capacitor, C now tries to charge to VCC through RC of Q1 and a small input resistance of Q2, as shown in Fig. 8.2. As t→∞, this voltage reaches VCC. To change the state of the devices, a trigger is applied at an appropriate point in the circuit.

FIGURE 8.1 The collector-coupled monostable multivibrator

FIGURE 8.2 The charging of capacitor C

#### 8.2.1 Triggering a Monostable Multivibrator

A trigger is a sharp positive or negative pulse of desired amplitude. A negative pulse may be applied at the base of the ON device to drive it into the OFF state or a positive pulse may be applied at the base of the OFF device to drive it into the ON state, as the devices used here are n–p–n devices. When a negative trigger is applied to drive an ON device into the OFF state, the instant the trigger is present; the base current of the device begins to reduce. However, when a positive trigger is applied to drive an OFF device into the ON state, the device will not draw any current till the amplitude of the pulse is Vγ. Thus, it is always preferable to drive an ON device into the OFF state rather than trying to drive an OFF device into the ON state, unless warranted otherwise. Obviously, the triggering sensitivity (ability to change state with a smaller pulse) is better if an ON device is driven into the OFF state rather than applying the other option. Therefore, we now try to drive Q2 into the OFF state by the application of a negative pulse at the base of Q2, which is ON and in saturation. The input resistance of Q2 is very small and hence, loads the trigger source. To avoid loading, the trigger may be applied as shown in Fig. 8.3.

The negative trigger, to drive Q2 OFF is now applied at the collector of Q1 through Ci and diode D1—which conducts only for negative trigger pulses. Rd is the resistance returned to VCC, which is the input resistance offered by the circuit to the trigger source. If Rd is small, it loads the trigger source. Therefore, here, Rd will have to be large. However, when D1 is ON, charge is built up on the condenser Ci, which should be quickly removed before the application of the next trigger pulse; thus, Rd should be small on this count. A single resistance cannot satisfy both these conflicting requirements. Hence, in place of the resistance Rd, D2 is connected, which satisfies both the requirements. When the trigger signal is present, D2 is OFF and offers large input resistance to the trigger source. When the trigger signal is not there, D2 conducts, offering negligible resistance so that the accumulated charge on condenser Ci is quickly removed. As C is connected between the first collector and second base, the trigger signal is instantaneously connected to B2.

#### 8.2.2 Calculation of the Time Period (T)

On the application of a trigger at t = 0, with a negative pulse at B2, Q2 goes into the OFF state and Q1 is driven into the ON state and preferably into saturation. Hence, there is a current I1 in Q1. VC1 is VCE(sat), if I1 = IC(sat), as shown in Fig. 8.4(a).

The charge on the capacitor C now decays with a time constant τ = RC, as shown in Fig. 8.4(b). Consequently, the voltage at B2 changes as a function of time and this voltage, VB2 at B2, reaches Vγ after a time interval T. The moment the voltage at B2 is once again Vγ, Q2 has a small base current, which in turn gives rise to collector current. Earlier the voltage at this collector was VCC as Q2 was OFF. Due to this collector current, the voltage at the collector of Q2 falls, giving rise to a negative step. This negative step is coupled to the base of Q1 through R1 and R2 and thus, the base current of Q1 reduces, reducing its collector current. The voltage at the first collector now rises (earlier it was VCE(sat)), resulting in a positive step. This change in voltage is coupled to the second base, increasing its base current further. As the collector current increases, the voltage at this collector reduces; this change in the voltage is once again coupled to the first base, reducing its base current further. Its collector current is now reduced, giving rise to a further increase in the voltage at the first collector, which once again is coupled to the second base. It is observed that regeneration takes place and Q2 is switched ON and Q1 is switched OFF, thus ending the quasi-stable state (also look at the voltage variation at B2 of Q2 shown in Fig. 8.5).

FIGURE 8.3 The triggering of a monostable multivibrator

FIGURE 8.4(a) When Q1 is ON, in the quasi-stable state

FIGURE 8.4(b) Discharge of C

FIGURE 8.5 The voltage variation at the base of Q2, in the quasi-stable state

We have from Eq. (7.1),

VB2(t) = vf − (vfvi)et/τ

Here, vf = VCC, and if Q1 is in saturation,

vi = VσI1RC = Vσ − [VCCVCE(sat)] = VσVCC + VCE(sat)

and the time constant, τ = RC

Using Eq. (7.1)

However, at t = T, VB2(t) = Vγ

Vγ = VCC − [2VCC − (Vσ + VCE(sat)]eT/τ1

As

The time period T can be calculated as T = 0.69 RC, if Q1 in the quasi-stable state is in saturation.

#### 8.2.3 The Effect of Temperature on Gate Width

If the temperature effects are not taken into consideration, the gate width of a collector-coupled monostable multivibrator is given as T = 0.69 τ. When the temperature changes are taken into consideration, this gate width is likely to change. Consider a transistor which is in the OFF state as shown in Fig. 8.6(a).

Ideally, IC = 0. However, there exists a leakage current called ICBO = ICO. The collector cut-off current, ICO is reasonably large in Ge devices, but is small in Si devices. For Si devices at room temperature (25°C), typically ICO is in the order of nanoamperes. However, as the temperature increases ICO also increases, and gets doubled for every 10°C rise in temperature. When IC = 0, VCE = VCC If ICO = 10 µA and RC = 2 kΩ, then

VCE = VCCICO RC = 10 − (0.01)(2) = 9.98 V

Thus, the voltage at the collector is 9.98 V instead of 10 V. In normal applications, this may not be important. However, in precision applications, temperature effects will have to be considered. Now consider the collector-coupled monostable multivibrator in Fig. 8.6(b). In the stable state, when capacitor C is fully charged, it behaves as an open circuit for dc. If the multivibrator is now driven into the quasi-stable state, the voltage to which the capacitor is returned is seen to be V = VCC + ICOR, instead of VCC. Hence, when capacitor C discharges, the final voltage vf = V.

Let us now calculate the time period. We have from Eq. (7.1):

VB2(t) = vf − (vfvi)et/τ

Here,

And if Q1 is in saturation,

vi = VσI1RC = Vσ − [(VCCVCE(sat)] = VσVCC + VCE(sat)

Neglecting the junction voltages vi = −VCC, and the time constant, τ = RC.      Using Eq. (7.1):

However, at t = T, VB2(t) = Vγ ≈ 0.

0 = V − (V + VCC)eT/τ

FIGURE 8.6(a) Transistor in the OFF state

FIGURE 8.6(b) The collector-coupled monostable multivibrator considering ICO

Substituing Eq. (8.3) in Eq. (8.6):

If

The gate width of the monostable multivibrator will now be less than the gate width calculated using Eq. (8.2). This effect can be more pronounced with Ge transistors and at elevated temperatures. Let us consider an example.

##### EXAMPLE

Example 8.1: Calculate the gate width for the monostable multivibrator given that R = 100 kΩ, VCC = 10 V, C = 0.01 µF;
(a) when ICO is neglected and (b) when ICO = 0.01 mA.

Solution:

1. τ = RC = 100 × 103 × 0.01 × 10−6 = 1 ms

When ICO is neglected, the gate width is calculated using Eq. (8.2),

T = 0.69 × 100 × 103 × 0.01 × 10−6 = 0.69 ms.

2. When ICO is considered, from Eq. (8.7),

τln(1.05) = 1 × 10−3 × 0.049 = 0.049 ms

Therefore, T when the leakage current is considered, using Eq. (8.8) is

T = 0.69 − 0.049 = 0.641 ms.