8.3 Calculation of the Voltages to Plot the Waveforms – Pulse and Digital Circuits

8.3 CALCULATION OF THE VOLTAGES TO PLOT THE WAVEFORMS

To plot the waveforms at the two collectors and the two bases, the voltages in the circuit are to be calculated; when the multivibrator is in the stable state, when it is driven into the quasi-stable state and finally when it returns to the initial stable state. Consider the collector-coupled monostable multivibrator as shown in Fig. 8.1.

8.3.1 In the Stable State (t < 0)

Here, the assumption is that Q2 is ON and in saturation while Q1 is OFF. In this situation, the need is to verify whether Q2 is really in saturation or not and whether Q1 is in the OFF state.

To Verify that Q2 is in Saturation. For this we need to calculate IC2 and IB2 and then verify whether IB2 is significantly larger than IB2 (min) or not. If IB2 >> IB2 (min), then Q2 is really in saturation. To verify this, consider the circuit shown in Fig. 8.7(a). From Fig. 8.7(a),

FIGURE 8.7(a) In the stable state Q1 is OFF and Q2 is ON

For Q2 to be in saturation, IB2 should be at least 1.5 IB2 (min). If IB2 >> IB2 (min), Q2 is really in saturation, as per the assumption made. Hence VC2 = VCE(sat) and VB2 = VBE(sat) = Vσ.

To Verify that Q1 is OFF. To show that Q1 is OFF, the voltage VB1 at B1 is to be found out and then checked whether the base–emitter diode is reverse-biased or not. If this diode is reverse-biased, then Q1 is OFF. To calculate the voltage VB1 at B1, consider the circuit shown in Fig. 8.7(b). The voltage VB1 is due to the two sources; the VBB source and the VCE(sat) source. Use the superposition theorem to calculate VB1, considering one source at a time. Shorting the VBB source, the resultant circuit is as shown in Fig. 8.7(c).

Now shorting the VCE(sat) source, the resultant circuit is as shown in Fig. 8.7(d).

Combining Eqs. (8.14) and (8.15), the net voltage VB1 at B1 due to the two sources VCE(sat) and −VBB is:

If the base of Q1 is negative with respect to the emitter, the base–emitter diode is reverse-biased. Therefore, Q1 is OFF, as assumed. Hence, VC1 = VCC. The voltage across the capacitor terminals is,

8.3.2 In the Quasi-stable State (t = 0+)

At t = 0, a negative pulse of proper amplitude is applied at the base of Q2 that drives Q2 into the OFF state. As a result Q1 goes into the ON state and into saturation as shown in Fig. 8.7(e).

FIGURE 8.7(b) The circuit for calculating VB1

FIGURE 8.7(c) The circuit to calculate VB1 due to VCE(sat) source

FIGURE 8.7(d) The circuit to calculate VB1 due to – VBB source

FIGURE 8.7(e) In the quasi-stable state Q1 is ON and Q2 is OFF

First let us verify whether Q1 is really in saturation or not. Let us calculate IC1.

To calculate IR, write the KVL equation of the loop consisting of RC, C and R.

Using Eqs. (8.19) and (8.20), we get I1 and IR.

Therefore,

To Calculate IB1. Considering Fig. 8.7(f):

If IB1 >> IB1(min), then Q1 is in saturation,

In the quasi-stable state, only VB2 changes and all other voltages remain unaltered. At t = T, when VB2 = Vγ, the quasi-stable state ends and the multivibrator returns to the initial stable condition of Q1 and Q2 in the OFF and ON states, respectively.

8.3.3 At the End of the Quasi-stable State (at t = T +)

At the end of the quasi-stable state, Q1 goes OFF and Q2 goes ON and into saturation. In this process, overshoots (increase over and above the expected value) can occur at the base of Q2 and at the collector of Q1, because the voltage change occurs abruptly. The amount of overshoot is accounted for by the base spreading resistance rbb which is the resistance seen between the external base lead and the internal base terminal and is the resistance offered to a recombination current. This is typically less than 1 kΩ, as shown in Fig. 8.7(g).

From Fig. 8.7(g),

As

Neglecting the current IR when compared to the circuit reduces to as shown in Fig. 8.7(h).

The voltages at B2 and C1 are

The overshoot δ at the second base is the variation over and above Vγ.

Using Eq. (8.30):

Similarly the overshoot δ at the first collector is the variation over and above VCE(sat)

Therefore,

Using Eq. (8.31):

FIGURE 8.7(f) Circuit that is used to calculate IB1

FIGURE 8.7(g) The circuit at the end of the quasi-stable state

FIGURE 8.7(h) The simplified circuit of Fig. 8.7(g)

The first collector and the second base are connected through a condenser C and as the condenser will not allow any sudden changes in the voltages, whatever is the change that takes place at the first collector an identical change is required to take place at the second base. Hence, δ = δ.

The waveforms can now be plotted. To plot the waveforms of a collector-coupled monostable multivibrator with specific component values mentioned, consider the following example.

EXAMPLE

Example 8.2: Consider the circuit shown in Fig. 8.8(a), which uses an npn silicon transistors with the following specifications: VCC = 10 V, VBB = 10 V, RC = 1 kΩ, R1 = 10 kΩ = R, R2 = 100 kΩ, hFE(min) = 30, rbb = 0.2 kΩ, VCE(sat) = 0.3 V, VBE(sat) = Vσ = 0.7 V. Calculate all the current and voltages and then plot the waveforms.

Solution: (i) In the stable state (t < 0)

The assumption made is Q2 is ON and in saturation and Q1 is OFF. To verify that Q2 is ON and in saturation, IC2 and IB2 of Q2 are to be calculated. Further check whether IB2 >> IB2 (min) or not. If IB2 >> IB2 (min), then Q2 is really in saturation. Consider the circuit shown in Fig. 8.8(b).

(a) To verify if Q2 is ON and in saturation:

FIGURE 8.8(a) Practical collector-coupled monostable multivibrator

FIGURE 8.8(b) In the stable state, Q1 is OFF and Q2 is ON

IC2 = I2I3 = 9.7 mA − 0.0934 mA = 9.61 mA

For Q2 to be in saturation, IB2 should be at least 1.5 IB2 (min). Hence, IB2 should be selected to keep Q2 in saturation as

 

IB2 = 1.5 × 0.32 mA = 0.48 mA.

As IB2(0.93 mA) >> 1.5IB2(min)(0.48 mA), as per the assumption made Q2 is really in saturation. Hence,

 

VC2 = 0.3 V, and VB2 = 0.7 V.

b) To verify that Q1 is OFF:

To verify whether Q1 is in the OFF state or not, VB1 = VBE1 is calculated and seen if it reverse-biases the base–emitter diode. The voltage VB1 is due to two sources—the VBB source and the VCE(sat) source, as shown in Fig. 8.8(c). Use the superposition theorem to calculate VB1, considering one source at a time. Considering the VCE(sat) source and shorting the VBB source, the resultant circuit is as shown in Fig. 8.8(d).

FIGURE 8.8(c) The circuit for calculating VB1

FIGURE 8.8(d) The circuit to calculate VB1 due to VCE(sat) source

Now shorting the VCE(sat) source, the resultant circuit is as shown in Fig. 8.8(e).

Therefore, the net voltage VB1 at B1 due to the two sources VCE(sat) and −VBB is

 

VB1 = 0.27 − 0.91 = −0.64 V.

This explains that the base of Q1 is negative with respect to the emitter by 0.64 V. Hence, the base–emitter diode is reverse-biased. Therefore, Q1 is OFF, as assumed. Hence, VC1 = VCC = 10 V. The voltage across the capacitor terminals is

 

VA = VC1VB2 = VCCV σ = 10 V − 0.7 V = 9.3 V

In the stable state, the voltages are VB1 = −0.64 V, VC1 = 10 V, VB2 = 0.7 V, VC2 = 0.3 V, VA = 9.3 V.

ii) In the quasi-stable state (t = 0+)

In the quasi-stable state, Q2 is driven into the OFF state, by the application of a trigger. Consequently, Q1 goes into the ON state and into saturation as shown in Fig. 8.8(f).

FIGURE 8.8(e) Circuit to calculate VB1 due to −VBB source

FIGURE 8.8(f) In the quasi-stable state, Q1 is ON and Q2 is OFF

a) To verify if Q1 is ON and in saturation or not

To verify whether Q1 is really in saturation or not, calculate IC1.

To calculate IR the KVL equation of the loop consisting of RC, C and R is,

 

IRR = I1RC + VA = 9.7 V + 9.3 V = 19 V       

Therefore,

IC1 = I1 + IR = 9.7 mA + 1.9 mA = 11.6 mA

To calculate IB1, consider Fig. 8.8(g).

 

IB1 = I3I4

IB1 = 0.84 − 0.11 = 0.73 mA

FIGURE 8.8(g) The circuit that is used to calculate IB1

As already calculated, IB1(min) = 0.39 mA. Thus, IB1 >> IB1(min).

Hence, Q1 is in saturation.

 

VC1 = 0.3 V, VB1 = 0.7 V,

VC2 = VCCI3RC = 10 − (0.84)(1) = 9.16 V (But for the current, I3, VC2 should have been 10 V)

 

VB2 = VCCIRR = 10 − (1.9)(10) = −9 V

In the quasi-stable state, except VB2—which changes exponentially as a function of time—all other voltages remain unaltered. At t = T, when VB2 = Vγ, the quasi-stable state ends and the multivibrator returns to its initial stable condition. The voltages at the beginning of the quasi-stable state are VC1 = 0.3 V, VB1 = 0.7 V, VC2 = 9.16 V, VB2 = −9 V initially and varies exponentially.

iii) At the end of the quasi-stable state (at t = T +)

At the end of the quasi-stable state Q1 goes OFF and Q2 goes ON and into saturation, resulting in overshoots at the base of Q2 and at the collector of Q1. The overshoots are calculated using Fig. 8.8(h).

Neglecting the current IR when compared to the circuit reduces to Fig. 8.8(i).

FIGURE 8.8(h) The circuit that is used to calculate IB1

FIGURE 8.8(i) The simplified circuit of Fig. 8.8(h)

FIGURE 8.8(j) Waveforms of the collector-coupled monostable

Using Eq. (8.34):

= 7.91 mA

= VCCRC = 10 − (7.91)(1)

= 2.09 V

= rbb′ + Vσ

      = (7.91)(0.2) + 0.7 = 1.58 + 0.7

= 2.28 V

At t = T+, the voltages are VC2 = 0.3 V, VB2 = 2.28 V, VC1 = 10 V, VB1 = −0.64 V. The waveforms are plotted as shown in Fig. 8.8(j).

8.3.4 The Design of a Collector-coupled Monostable Multivibrator

Let us design a collector-coupled monostable multivibrator of Fig. 8.1, having a gate width T. From the circuit of Fig. 8.1 we have,

Select IB(sat) = 2 × IB(min)

For ON device to be in saturation:

On verifying whether the condition in Eq. (8.40) is satisfied or not; the value of R is accepted (if satisfying). If not, the value of R is changed suitably, to satisfy the Eq. (8.40).

Assuming that the current in R2 is I2:

When Q1 is ON, if I1 is the current in (RC + R1):

R1 = (RC + R1) − RC

Using the relation, T = 0.69RC, the value of C is calculated. To understand the design procedure let us consider an example.

EXAMPLE

Example 8.3: Design a collector-coupled monostable circuit of Fig. 8.1 to generate a pulse of width 100 µs. Silicon devices with hFE(min) = 50 are used. ON device is in saturation.

Given that:

  VCC = 12 V, VCE(sat) = 0.2 V, VBE(sat) = 0.7 V, IB(sat) = 2 IB(min), VBB = 12 V, IC(sat) = 2 mA, T = 100 µs.

Solution:

  1. Let Q2 be ON and Q1 be OFF.

    IB2(sat) = 2 × IB2 (min) = 2 × 40 = 80 µA

    hFERC = 50 × 6 = 300 kΩ

    For ON device to be in saturation,

     

    Rh FERC

    Hence, the condition is verified.

  2. When Q1 is ON, let I2 be the current in R2.

    Let I1 be the current in RC + R1.

     

    I1 = IB1 + I2 = 0.08 + 0.2 = 0.28 mA

    R1 = (RC + R1) − RC = 40 − 6 = 34 kΩ

    T = 0.69RC     100 × 10−6 s = 0.69 × 141 × 103 × C