APPENDIX 1. The PIC 16 Series instruction set – Designing Embedded Systems with PIC Microcontrollers, 2nd Edition

APPENDIX 1. The PIC 16 Series instruction set
TABLE A1.1. PIC 16 Series Instruction Set Summary

Mnemonic, operandsDescriptionCycles14-Bit opcodeStatus affectedNotes
ADDWFf,dAdd W and f1000111dfffffffC,DC,Z1,2
ANDWFf,dAND W with f1000101dfffffffZ1,2
CLRFfClear f1000001lfffffffZ2
CLRW-Clear W10000010xxxxxxxZ
COMFf,dComplement f1001001dfffffffZ1,2
DECFf,dDecrement f1000011dfffffffZ1,2
DECFSZf,dDecrement f, Skip if 01(2)001011dfffffff1,2,3
INCFf,dIncrement f1001010dfffffffZ1,2
INCFSZf,dIncrement f, Skip if 01(2)001111dfffffff1,2,3
IORWFf,dInclusive OR W with f1000100dfffffffZ1,2
MOVWfMove W to f1000000lfffffff
NOP-No Operation10000000xx00000
RLFf,dRotate Left f through Carry1001101dfffffffC1,2
RRFf,dRotate Right f through Carry1001100dfffffffC1,2
SUBWFf,dSubtract W from f1000010dfffffffC,DC,Z1,2
SWAPFf,dSwap nibbles in f1001110dfffffff1,2
XORWFf,dExclusive OR W with f1000110dfffffffZ1,2
BCFf,bBit Clear f10100bbbfffffff1,2
BSFf,bBit Set f1010lbbbfffffff1,2
BTFSCf,bBit Test f, Skip if Clear1(2)01l0bbbfffffff3
BTFSSf,bBit Test f, Skip if Set1(2)01llbbbfffffff3
ADDLWkAdd literal and W111lllxkkkkkkC,DC,Z
ANDLWkAND literal with W1111001kkkkkkZ
CALLkCall subroutine2100kkkkkkkkk
CLRWDT-Clear Watchdog Timer100000001100100TO.PD
GOTOkGo to address210lkkkkkkkkk
IORLWkInclusive OR literal with W1111000kkkkkkZ
MOVLkMove literal to W11100xxkkkkkk
RETFIE-Return from interrupt200000000001001
RETLWkReturn with literal in W2110lxxkkkkkk
RETURN-Return from Subroutine200000000001000
SLEEP-Go into standby mode100000001100011TO.PD
SUBLWkSubtract W from literal111110xkkkkkkC.DC.Z
XORLWkExclusive OR literal with W1111010kkkkkkZ
Note 1: When an I/O register is modified as a function of itself (e.g., movf portb, ·1), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer 0 module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a nop.