APPENDIX 5. The PIC 18 Series instruction set – Designing Embedded Systems with PIC Microcontrollers, 2nd Edition

APPENDIX 5. The PIC 18 Series instruction set
TABLE A5.1. The PIC 18 Series Standard Instruction Set Summary

Mnemonic, operandsDescriptionCycles16-bit instruction wordStatus affectedNotes
ADDWFf,d,aAdd WREG and f001001da0ffffffffC, DC, Z, OV, N1,2
ADDWFCf,d,aAdd WREG and Carry bit to f00100daffffffffC, DC, Z, OV, N1,2
ANDWFf,d,aAND WREG with f000101daffffffffZ, N1,2
CLRFf,aClear f0110101affffffffZ2
COMFf,d,aComplement f000111daffffffffZ, N1,2
CPFSEQf,aCompare f with WREG, skip =1 (2 or 3)0110001affffffffNone4
CPFSGTf,aCompare f with WREG, skip >1 (2 or 3)0110010affffffffNone4
CPFSLTf,aCompare f with WREG, skip <1 (2 or 3)0110000affffffffNone1,2
DECFf,d,aDecrement f000001daffffffffC, DC, Z, OV, N1,2,3,4
DECFSZf,d,aDecrement f, Skip if 01 (2 or 3)001011daffffffffNone1,2,3,4
DCFSNZf,d,aDecrement f, Skip if Not 01 (2 or 3)010011daffffffffNone1,2
INCFf,d,aIncrement f001010daffffffffC, DC, Z, OV, N1,2,3,4
INCFSZf,d,aIncrement f, Skip if 01 (2 or 3)001111daffffffffNone4
INFSNZf,d,aIncrement f, Skip if Not 01 (2 or 3)010010daffffffffNone1,2
IORWFf,d,aInclusive OR WREG with f000100daffffffffZ, N1,2
MOVFf,d,aMove f010100daffffffffZ, N1
MOVFFfs,fdMove fs (source) to 1st word21100ffffffffffffNone
fd (destination) 2nd word1111ffffffffffff
MOVWFf,aMove WREG to f0110111affffffffNone
MULWFf,aMultiply WREG with f0000001affffffffNone
NEGFf,aNegate f0110110affffffffC, DC, Z, OV, N1,2
RLCFf,d,aRotate Left f through Carry001101daffffffffC,Z, N
RLNCFf,d,aRotate Left f (No Carry)010001daffffffffZ, N1,2
RRCFf,d,aRotate Right f through Carry001100daffffffffC, Z,N
RRNCFf,d,aRotate Right f (No Carry)010000daffffffffZ, N
SETFf,aSet f0110100affffffffNone
SUBFWBf,d,aSubtract f from WREG with borrow010101daffffffffC, DC, Z, OV, N1,2
SUBWFf,d,aSubtract WREG from f010111daffffffffC, DC, Z, OV, N
SUBWFBf,d,aSubtract WREG from f with borrow010110daffffffffC, DC, Z, OV, N1,2
SWAPFf,d,aSwap nibbles in f001110daffffffffNone4
TSTFSZf,aTest f, skip if 01 (2 or 3)0110011affffffffNone1,2
XORWFf,d,aExclusive OR WREG with f000110daffffffffZ, N
BCFf,b,aBit Clear f1001bbbaffffffffNone1,2
BSFf,b,aBit Set f1000bbbaffffffffNone1,2
BTFSCf,b,aBit Test f, Skip if Clear1 (2 or 3)1011bbbaffffffffNone3,4
BTFSSf,b,aBit Test f, Skip if Set1 (2 or 3)1010bbbaffffffffNone3,4
BTGf,d,aBit Toggle f0111bbbaffffffffNone1,2
BCnBranch if Carry~U2)11100010nnnnnnnnNone
BNnBranch if Negative1(2)11100110nnnnnnnnNone
BNCnBranch if Not Carry1(2)11100011nnnnnnnnNone
BNNnBranch if Not Negative1(2)11100111nnnnnnnnNone
BNOVnBranch if Not Overflow1(2)11100101nnnnnnnnNone
BNZnBranch if Not Zero211100001nnnnnnnnNone
BOVnBranch if Overflow1(2)11100100nnnnnnnnNone
BRAnBranch Unconditionally1(2)11010nnnnnnnnnnnNone
BZnBranch if Zero1(2)11100000nnnnnnnnNone
CALLn,sCall subroutine 1st word21110110skkkkkkkkNone
2nd word1111kkkkkkkkkkkk
CLRWDTClear Watchdog Timer10000000000000100TO, PD
DAWDecimal Adjust WREG10000000000000111C
GOTOnGo to address 1st word211101111kkkkkkkkNone
2nd word1111kkkkkkkkkkkk
NOPNo Operation10000000000000000None
NOPNo Operation11111xxxxxxxxxxxxNone4
POPPop top of return stack (TOS)10000000000000110None
PUSHPush top of return stack (TOS)10000000000000101None
RCALLnRelative Call211011nnnnnnnnnnnNone
RESETSoftware device RESET10000000011111111All
RETFIEsReturn from interrupt enable2000000000001000sGIE/GIEH, PEIE/GIEL
RETLWkReturn with literal in WREG200001100kkkkkkkkNone
RETURNsReturn from Subroutine2000000000001001sNone
SLEEPGo into Standby modeJ0000000000000011TO, PD
ADDLWkAdd literal and WREG100001111kkkkkkkkC, DC, Z, OV, N
ANDLWkAND literal with WREG100001011kkkkkkkkZ, N
IORLWkInclusive OR literal with WREG100001001kkkkkkkkZ, N
LFSRf,kMove literal (12-bit) 2nd word21110111000ffkkkkNone
MOVLBkMove literal to BSR<3:0>1000000010000kkkkNone
MOVLWkMove literal to WREG100001110kkkkkkkkNone
MULLWkMultiply literal with WREG100001101kkkkkkkkNone
RETLWkReturn with literal in WREG200001100kkkkkkkkNone
SUBLWkSubtract WREG from literal100001000kkkkkkkkC, DC, Z, OV, N
XORLWkExclusive OR literal with WREG100001010kkkkkkkkZ, N
TBLRDTable Read20000000000001000None
TBLRD+Table Read with post-increment0000000000001001None
TBLRD-Table Read with post-decrement0000000000001010None
TBLRD+Table Read with pre-increment0000000000001011None
TBLWTTable Write2(5)0000000000001100None
TBLWT+Table Write with post-increment0000000000001101None
TBLWT-Table Write with post-decrement0000000000001110None
TBLWT+Table Write with pre-increment0000000000001111None
Note 1: When a PORT register is modified as a function of itself (e.g., movf portb, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a nop.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a nop, unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.
5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated.
TABLE A5.2. Summary of opcode operand symbols

SymbolDescription (MPLAB Assembler default value underlined)
RAM Access bit.
a = 0: Memory location is in Access RAM.
a = 1: RAM Bank specified by Bank Select Register (BSR) .
bBit number in byte.
Destination select bit.
d = 0: result stored in W register.
d = 1: result stored in file register f (i.e. data memory location).
f8-bit data memory address.
fd12-bit data memory address, destination address in a data move.
fs12-bit data memory address, source address in a data move.
kLiteral value, constant data or label (8, 12 or 20-bit).
nRelative address (two’s complement) for relative branch instructions, OR direct address for Call and Return instructions.
Fast Call/Return mode select bit.
s = 0: do not update into or from shadow registers.
s = 1: update W, Status and BSR registers into or from shadow registers.
If the ‘a’ bit is not specified, the Assembler may also determine it depending on the memory location being addressed.
TABLE A5.3. Extensions to the PIC 18 Series Instruction Set

Mnemonic, operandsDescriptionCycles16-Bit instruction wordStatus affected
ADDFSRf, kAdd Literal to FSR111101000ffkkkkkkNone
ADDULNkkAdd Literal to FSR2 and Return21110100011kkkkkkNone
CALLWCall Subroutine using WREG20000000000010100None
MOVSFZs, fdMove Zs (source) to 1st word2111010110zzzzzzzNone
fd (destination) 2nd word1111ffffffffffffNone
MOVSSZs, ZdMove Zs (source) to 1st word2111010111zzzzzzz
Zd (destination) 2nd word1110xxxxxzzzzzzzNone
PUSHLkStore Literal at FSR2, Decrement FSR2111101010kkkkkkkkNone
SUBFSRf, kSubtract Literal from FSR111101001ffkkkkkkNone
SUBULNKkSubtract Literal from FSR2 and Return21110100111kkkkkkNone