## Chapter 11

## First-Order *RC* Circuits

##### CHAPTER OBJECTIVES

*Impulse,Step and Ramp Response of First-Order RC Circuits**Series RC Circuit with Real Exponential Input**Zero-State Response of Parallel RC Circuit for Sinusoidal Input**The Use of Frequency Response and Linear Distortion**First-Order RC Circuits as Averaging Circuits**Capacitor as a Signal Coupling and Signal Bypassing Element*

##### INTRODUCTION

A circuit containing a single linear time-invariant capacitor and a linear time-invariant resistor, excited by a voltage source in series or a current source in parallel, will constitute a first-order LTI circuit. We have studied a first-order circuit – namely, the* RL* Circuit – in great detail and used it to bring out all the important concepts in the time-domain analysis of electrical circuits in the last chapter. Hence, we will be able to move through simple* RC* circuits rather quickly in this chapter. That does not mean that* RC* circuits are less important in any sense compared to* RL* circuits.* RL, RC* and* RLC* circuits are basic building blocks of electrical and electronic circuits and are equally important. It is only that we chose to deal with* RL* circuits first and that in no way makes other dynamic circuits less important.

##### 11.1 *RC* CIRCUIT EQUATIONS

First-order Series* RC* Circuit and Parallel* RC* Circuit are shown in Fig. 11.1-1 with all element variables identified. We choose the voltage across capacitor, *v*_{C}(*t*), as the describing variable in both cases. If *v*_{C}(*t*) is known in the series circuit, the current through capacitor can be obtained by multiplying the first derivative of *v*_{C}(*t*) by *C*. Then the current through the resistor and voltage across it may be found. Similarly, all other element variables in the Parallel* RC* Circuit can be found out if *v*_{C}(*t*) in that circuit is known.

**Fig. 11.1-1** 1(a) The series *RC* circuit (b) The parallel *RC* circuit

The differential equation governing the Series* RC* Circuit is obtained by applying KCL at the positive terminal of the capacitor along with element equations of resistor and capacitor.

The differential equation for the Parallel* RC* Circuit is obtained by applying KCL at the positive terminal of the capacitor.

The describing differential equation is a linear first-order equation with constant coefficients in both the cases. We expect the solution to contain a natural response term of* e ^{–αt}* type with

*α*= 1/

*RC*. Comparing with the

*RL*circuit equations, we can identify the time constant of

*RC*circuit as

*RC*seconds.

##### 11.2 ZERO-INPUT RESPONSE OF *RC* CIRCUIT

The differential equations derived above can be used to solve for *v*_{C}(*t*) for all* t* provided the input source function is known for all *t*. However, we do not know the input source function for all *t*. The input source function is usually known only for* t* > 0. It may contain a discontinuity at* t =* 0 too. The input source function is generally unknown for* t* < 0.

Therefore, the effect of all the unknown currents which went through the capacitor from infinite past to* t =* 0^{−} is given in a condensed manner in the form of an initial value specification for *v*_{C}(*t*) at* t =* 0^{–}. Let us denote this value as *V*_{o}. Now we can obtain the total response of the circuit by adding the two response components – zero-input response and zero-state response.

*Zero-input response* is the response for* t *≥ 0^{+} when the input is held at zero from* t =* 0 onwards.* Zero-state response* is the response for* t *≥ 0^{+} when the input is held zero from infinite past to* t =* 0^{–} (or equivalently, initial condition at* t =* 0^{–} is 0) and then a specified input source function is applied from* t* = 0 onwards.

Zero-input response is the same as the so-called* source-free response.* The describing differential equation in this situation is

Physically this amounts to connecting a charged capacitor to a resistor to form a closed loop at *t* = 0. The initial voltage across the capacitor appears across the resistor from* t* = 0 onwards. The resistor demands a current of *v*_{C}(*t*)/*R* and this current flow is of suitable polarity to discharge the capacitor. As the capacitor discharges more and more, its voltage comes down, resulting in the discharge current also going down. Thus the capacitor keeps discharging; but at slower and slower rates as time increases. The discharge current divided by capacitance value gives rate of decrease of voltage across the capacitor. Hence, the initial rate of decrease of voltage is *V*_{o}/*τ* V/s, where *τ* is the time constant (=*RC*) of the circuit. If the initial rate of decrease were maintained throughout, the voltage across capacitor would have gone to zero in one time constant.

There was no impulse current source in this circuit and hence the voltage across capacitor does not change instantaneously at* t* = 0. Hence *v*_{C}(*t*) at* t* = 0^{+} is same as *v*_{C}(*t*) at* t* = 0^{–},* i.e.,* *V*_{o}. Therefore, the expression for *v*_{C}(*t*) is given by the familiar exponential function.

The graph of this function is only too well known and is not repeated here.

**Example: 11.2-1**

Practical dielectrics employed in capacitors have non-zero volume conductivity and surface conductivity. This results in a* leakage current* that tends to discharge an initially charged capacitor even when it is left open. This phenomenon is called* self-discharge* of a capacitor. A 1000*μ*F Electrolytic capacitor is charged to 400 V and is left open from* t* = 0 onwards. The voltage across capacitor is found to be 40 V at* t* = 10 minutes. What will be the power dissipated in the capacitor if it is connected across a 400 V DC source for a long time?

**Solution**

The capacitor discharges due to its internal leakage current. This leakage current may be modelled approximately by a resistor in parallel with the capacitor. Hence the charged capacitor undergoes the zero-input response of an* RC* circuit with a time constant of* RC,* where* R* is its shunt resistance equivalent to its self-discharge. The value of* R* is to be found out. Using Eqn. 11.2-2 with *V*_{o} = 400 V and *v*_{C}(*t*) = 40 V,

Now, if this capacitor is connected across a 400V DC source, this resistor will draw a current of 1.54 mA of current from the source. Hence, the power dissipated by the capacitor when it is connected across a 400V source will be 400 V × 1.54 mA = 0.616 W.

**Example: 11.2-2**

A capacitor* C* is initially charged to 500 V and is left open for 120 s. The voltage across the capacitor at the end of this time interval is seen to be 400 V. A resistor of 100 kΩ is connected across this capacitor at 120 s. The voltage across the capacitor is found to reach 100 V in 216.4 s after this connection has been made. Find the value of* C* and its leakage resistance.

**Solution**

Let* R* be the leakage resistance of the capacitor. Then, using Eqn. 11.2-2 with suitable values for* V _{o }* and

*v*

_{C}(

*t*),

##### 11.3 ZERO-STATE RESPONSE OF *RC* CIRCUITS FOR VARIOUS INPUTS

We consider the response of Series* RC* Circuit and Parallel* RC* Circuit for various input source functions in this section. We know that the total response of any circuit to application of input function is obtained by adding the zero-input response and zero-state response together. Hence we consider only the zero-state response part for various input source functions in this section. We begin with impulse response first.

#### 11.3.1 Impulse Response of First-Order *RC* Circuits

The Series* RC* Circuit in Fig. 11.3-1 (a) is excited by a unit impulse voltage source. The capacitor cannot absorb the impulse voltage. Hence the resistor absorbs the impulse voltage and as a result an impulse current containing 1/*R* Coulombs of charge flows through the circuit. This impulse current flow results in sudden dumping of 1/*R* Coulombs of charge on the capacitor plates thereby changing the capacitor voltage from 0 at* t* = 0^{–} to 1/*RC* V at* t* = 0^{+}. The unit impulse voltage source is a short circuit for* t *≥ 0^{+}. Therefore, the only effect of impulse voltage application is to change the initial condition of the capacitor instantaneously. The circuit effectively becomes a* source-free* circuit with initial energy for* t *≥ 0^{+} and executes its zero-input response. The relevant circuit is shown in of Fig. 11.3-1 (b).

**Fig. 11.3-1** Impulse response of series *RC* circuit

Initial voltage across capacitor is 1/*RC* V and all the voltages and currents in the circuit decay exponentially to zero with a time constant of *τ = RC* s.

We had noticed the equivalence between nonzero initial condition at* t =* 0^{–} and the application of impulse at* t =* 0 in our analysis of* RL* Circuits. We see that it is true in the case of* RC* circuits too. Specifically, a capacitor with an initial voltage of *V*_{o }V across it at* t =* 0^{–} may be replaced by a capacitor with zero initial voltage and a impulse current source of suitable magnitude (*CV*_{o} Coulombs) and polarity connected across it. This equivalence is shown in Fig. 11.3-2.

**Fig. 11.3-2** Equivalence between non-zero initial voltage and impulse current application in* RC* circuits

Figure. 11.3-3 shows the application of a unit impulse current to a parallel* RC* circuit. The resistor cannot support the impulse current. If it were to do so, it would have called for an impulse voltage across it and that will be resisted by the capacitor in parallel. Therefore, all the impulse content goes through the capacitor, changing its voltage by 1/*C* V instantaneously from 0 at* t =* 0^{–} to 1/*C* V at* t =* 0^{+}. The unit impulse current source is effectively an open-circuit after* t* = 0^{+}. Therefore, the circuit becomes a* source-free* circuit for* t *≥ 0^{+} and executes its zero-input response (in Fig. 11.3-3 (b)).

**Fig. 11.3-3** Unit impulse response of parallel *RC* circuit

Therefore,

**Example: 11.3-1**

The value of* I* in the circuit in Fig. 11.3-4 is 3 × 10^{–6} Coulombs. Find the zero-state response for the current through the 10k resistor in the direction marked in the figure.

**Fig. 11.3-4** Circuit for Example: 11.3-1

**Solution**

The voltage across the capacitor can, at best, change by a* finite* amount as a result of impulse current flow. This implies that the current through the 5k resistor across the capacitor cannot be an impulse. Therefore, the capacitor effectively shorts the 5k resistor across it as far as the impulse current flow is concerned. Hence the 3 × 10^{–6}*δ* (*t*) gets shared by 10k and the other 5k as per the current division principle in parallel resistors. Thus 2 × 10^{–6}*δ* (*t*) goes through the other 5k resistor and the 0.1*μ*F capacitor. This results in sudden dumping of 2*μ*C of charge across the capacitor, raising its voltage to 20 V at* t =* 0^{+}. The current source goes open for* t =* 0^{+} and the circuit executes its zero-input response.

Time constant of the circuit can be found by obtaining the equivalent resistance connected across the capacitor. The equivalent resistance is 5k//15k = 3.75k. Therefore, *τ* = 0.375 ms. The discharge current from the capacitor at 0^{+} is 20 V/3.75 kΩ = 5.333 mA and 20 V/15 kΩ = 1.333 mA of it goes through the 10k in the direction marked at that instant. Therefore, the zero-state response of this current for* I**δ* (*t*) current excitation at input of the circuit = 1.333 *e*^{–2666.67t} mA.

#### 11.3.2 Step Response of First-Order *RC* Circuits

*Step Response* is understood to be the zero-state response of the circuit when unit step input is applied to it. Hence the initial voltage across the capacitor is zero. It takes an impulse current flow through a capacitor to change its voltage by a non-zero finite amount instantaneously. Since there is no such impulse current flow in the present instance, the voltage across the capacitor remains zero at* t =* 0^{+} too.

Consider the Series* RC* Circuit first. The applied voltage at* t* = 0^{+} is 1 V and the voltage across the capacitor is constrained to remain at zero at that instant. And the circuit has to obey Kirchhoff’s Voltage Law at that instant. This implies that the voltage across the resistor at that instant has to be 1 V and that a current of 1/*R* A has to flow through the circuit at that instant. Since the rate of growth of a capacitor voltage is given by the charging current divided by capacitance value, the rate of change of *v*_{C}(*t*) at* t =* 0^{+} will be 1/*RC* V/s. As the capacitor voltage grows, the voltage available across the resistor decreases; thereby bringing down the charging current in the circuit. Hence the capacitor keeps charging up with progressively decreasing rate. This is a typical first-order process. The capacitor voltage tends to reach 1 V as* t* → ∞ and correspondingly the current through the circuit tends to go to zero.

The detailed solution may be worked out by either* ‘complementary solution plus particular integral’ *format or* ‘zero-input response plus zero-state response’ *format. But we can do better than that. We have already worked out the impulse response of the Series* RC* Circuit in this section. And we remember that for a* lumped linear time-invariant* circuit, the zero-state response gets integrated when the input source function gets integrated. Unit step function is the integral of Unit impulse function. Therefore,* step response* must be the integral of* impulse response.*

Therefore,

Now consider the Parallel* RC* Circuit excited by a unit step current source. The voltage across the capacitor at* t* = 0^{+} remains at zero. Therefore all of the source current,* i.e.,* 1 A has to flow through the capacitor. This results in charging up of capacitor with an initial charging rate of 1*/C* V/s As the capacitor gets charged, the resistor takes its share of current and consequently the rate of rise of voltage comes down. Now we may write down the circuit solution straightaway – *v*_{C}(*t*) must be a rising exponential tending towards* R* V, *i*_{C}(*t*) must be a decreasing exponential starting at 1 A and *i*_{R}(*t*) must be a rising exponential moving to 1 A. All of them will have the same time constant of *τ* =* RC* s.

These step response waveforms are plotted in Fig. 11.3-5.

**Fig. 11.3-5** Unit step response of *RC* circuits (a) Series* RC* circuit (b) parallel *RC* circuit

The zero-state responses in both cases contain a transient term (exponential in nature) and a steady-state response term (constant in nature). We had termed the steady-state response term as the* DC steady-state term* earlier. Since the current in a capacitor is proportional to the rate of change of its voltage, the only value of current such that both voltage and current in a capacitor remain constant in time is* zero.* It can have any constant voltage across it; but its current is constrained to be zero under DC steady-state.

A capacitor may be replaced by an open-circuit for the analysis of DC steady-state response.

The DC steady-state current in a Series* RC* Circuit is zero. This implies that there is energy flow from the DC source only during the charging process. After the capacitor has charged up fully there is no energy drain from the source. Consider the charging of a capacitor to* V *Volts in a Series* RC* Circuit using a DC source of* V* Volts.

Thus, the energy spent in charging up a capacitor to* V* is* CV ^{2}* Joules – half of which appears in the capacitor as electrostatic energy storage and the remaining half gets dissipated in the charging resistor.

*This conclusion is independent of the value of resistance of the resistor.*However, we should not stretch it to the case where

*R*= 0! That is when all those

*parasitic elements*that we neglected in modelling a real physical electrical device as a mathematical capacitance will start having their say in the matter.

#### 11.3.3 Ramp Response of Series *RC* Circuit

Here too we employ the integration method to arrive at the zero-state response to unit ramp input from the zero-state response to unit step input since unit ramp waveform is the integral of unit step waveform.

Ramp waveform finds application in many contexts in electronics, instrumentation and signal processing. It is used as the internal time-base waveform in oscilloscopes. It is used in timing and counting applications too. Some dedicated electronic circuitry generates this ramp waveform and the generated waveform is conducted to the application circuit by means of a two-wire connection. This two-wire connection can often be modelled approximately by a Series* RC* Circuit where the resistor is contributed by the output resistance of the generator circuit (*i.e.,* the resistor that appears in the Thevenin’s equivalent of the generator circuit output) and the capacitor is contributed by the input capacitance of the application circuit. The ramp waveform gets modified in this process of transmission from the output of generator circuit to the input of the application circuit. We observe from the above expression for ramp response of Series* RC* Circuit that the ramp waveform suffers two modifications – in the initial portion,* i.e.,* for* t* << *τ*, the output fails to follow the linear variation of input and is rather prominently an exponential waveform. For* t* >> *τ* the output follows the input; but with a constant difference of* τ* V. Hence, we may conclude that a Series* RC* Circuit will be able to transmit a ramp waveform more or less faithfully if the waveform duration is significantly larger than the time constant of the circuit. The waveforms in Fig. 11.3-6 show this clearly.

**Fig. 11.3-6** Unit ramp response of series *RC* circuit

#### 11.3.4 Series *RC* Circuit with Real Exponential Input

Consider a Series* RC* Circuit excited at the input by a real exponential voltage source of the form *v*_{S}(*t*) =* e ^{–σt} u*(

*t*) V. The zero-state response under real exponential excitation in the case of a Series

*RL*circuit was described in Section 10.8 in Chapter 10. The reader is referred to Eqn. 10.8-5 in Chapter 10. The zero-state response of capacitor voltage in the present case is written down by analogy from that equation as

This may also be written as

in terms of circuit time constant and excitation time constant.

The input source functions and corresponding capacitor voltage waveforms are shown in Fig. 11.3-7. Time is normalised to the base of circuit time constant in this figure.

**Fig. 11.3-7** Zero-state response of *RC* circuit for exponential input (a) Input wave (b) Capacitor voltage

The case with* α = σ* was avoided in Chapter 10 with a promise that it will be taken up later in a different context. We do not avoid it any longer. The case with* α = σ* is taken up now as a limiting case of Eqn. 11.3-1 as* α → σ*.

It may be verified by long division that,

The waveshape of output voltage will be the same as in Fig. 11.3-7. The output in this case will reach a maximum of 1/*e* = 0.3678 V at* t* = *τ* s.

Two first-order Series* RC* Circuits are cascaded using a unity gain buffer amplifier as shown in Fig. 11.3-8. Find the output *v*_{o}(*t*) as a function of time.

**Fig. 11.3-8** Circuit for Example: 11.3-2

**Solution**

The unity gain buffer amplifier in between prevents any interaction between the two* RC* circuits. This implies that the response of the first* RC* stage is independent of the presence of the second stage. The first stage produces a voltage across its capacitor that is accepted by second stage as its input source function as if it is coming from an ideal independent voltage source. Let *v*_{1}(*t*) be the response voltage at the terminals of the first capacitor. Then *v*_{1}(*t*) is twice the zero-state response to unit step input (*i.e.,* step response).The time constant of first stage is 10kΩ × 10*μ*F = 100ms = 0.1 s.

*v*

_{1}(

*t*) = 2(1 –

*e*

^{–10}

*) V for*

^{t}*t*≥ 0

^{+}

This voltage is the input to the second stage since the gain of the buffer amplifier is unity. This input may be treated as the sum of two inputs – 2*u*(*t*) and –2*e*^{–10t} *u*(*t*). Zero-state response of a lumped linear time-invariant circuit obeys superposition principle and hence the responses to these inputs may be found out individually and be superposed to get the desired response.

The time constant of the second stage is 20kΩ × 10*μ*F = 200ms = 0.2 s. The component contributed to *v*_{o}(*t*) by 2*u*(*t*) is 2(1–*e*^{–5t}) V. The contribution to *v*_{o}(*t*) by –2*e*^{–10t} *u*(*t*) is obtained by using Eqn. 11.3-1 with* α =* 5 and* σ =* 10. This contribution is – 2 × –(*e*^{–10t} – *e*^{–5t}) V for* t *≥ 0^{+}.

The first stage and second stage output voltage waveforms are shown in Fig. 11.3-9.

**Fig. 11.3-9** Output waveforms across *RC* stage capacitors in Example: 11.3-2

Two first-order Series* RC* Circuits are cascaded non-interactively by employing a unity gain buffer amplifier as shown in Fig. 11.3-10. The voltage across the resistor of the first* RC* stage is the input to the second stage and the voltage across the capacitor of the second stage is the desired output. Find the step response of the system.

**Fig. 11.3-10** Circuit for Example: 11.3-3

**Solution**

Let *v*_{1}(*t*) be the voltage across the 10kΩ resistor in the first stage. We know that the zero-state step response of capacitor voltage in a Series* RC* Circuit is (1 – *e ^{–}*

^{t/τ}), where

*τ*is the time constant of the circuit given by

*RC*product. The voltage across the capacitor and the voltage across resistor will have to add up to 1 V for all

*t*≤ 0

^{+}in step response of a Series

*RC*Circuit. Therefore, the step response of voltage across the 10kΩ resistor is [1 – (1 –

*e*

^{–t/}^{τ})] =

*e*

^{–t/τ}^{ }V. The time constant of the first stage is 0.1 s.

*v*

_{1}(

*t*) =

*e*

^{–10t}V for

*t*≥ 0

^{+}

This voltage is the input to the second stage. Its time constant is 0.01 s. We use Eqn. 11.3-1 to obtain *v*_{o}(*t*) with* α =* 100 and *σ* = 10.

Note that the steady-state value of step response is zero. This is so because the first capacitor effectively opens the circuit for DC under steady-state. All the DC content of the source voltage will be found across the first capacitor in the steady-state.

**Example: 11.3-4**

Show that the two circuits shown of Fig. 11.3-11 (a) and (b) have the same step response except for a sign change. The operational amplifier may be treated as an ideal one. Compare the currents drawn from the voltage source by the circuits.

**Fig. 11.3-11** Circuits for Example: 11.3-4

The time constant of the circuit in Fig. 11.3-11 (a) is 100 ms = 0.1 s and its step response is (1 – *e*^{–10t}) V for* t* ≥ 0^{+}.

Consider the circuit in (b). The Opamp is connected with negative feedback and we further assume that the input voltage applied is of such magnitude that the Opamp does not enter voltage saturation at its output. Moreover, we assume that the Opamp has sufficiently large slew rate capability such that it never enters rate-limited operation. With these assumptions, we can analyse the Opamp using its ideal model.

The non-inverting terminal of Opamp is grounded and by* virtual short* principle the inverting input terminal is also* virtually grounded.* Therefore, the current that flows through *R*_{1} is *u*(*t*)/*R*_{1}. Since the current into the input terminals of an ideal Opamp is zero, this current flows into the *R*_{2}//*C* combination connected in the feedback path of the Opamp. The voltage developed across this parallel combination is nothing but a scaled version of the step response of a Parallel* RC* Circuit with step current excitation. The scaling factor is 1/*R*_{1}. This step response is *R*_{2}(1 – e^{–10t}) since the time constant involved is 0.1 s. Therefore, the voltage developed across the parallel combination in the feedback path is (*R*_{2}/*R*_{1}) (1 – *e*^{–10t}) V with its positive polarity at the inverting input of operational amplifier. Since the inverting input is at* virtual ground,* the voltage of output terminal with respect to ground (reference point) is the negative of this voltage.

Therefore, the two circuits in Fig. 11.3-11 have the same step response (and hence same dynamic behaviour) except for a change in sign.

The voltage across* R* in the circuit of Fig. 11.3-11 (a) is [1 – (1 – *e*^{–10t})] = *e*^{–10t} V and therefore the current drawn from the unit step voltage source by this circuit is 0.1 *e*^{–10t} mA for* t* ≥ 0^{+}. But the current drawn by the second circuit is *u*(*t*)/*R*_{1} = 0.1 mA for* t *≥ 0^{+} . Thus, the second circuit presents a constant input resistance level to the applied voltage source whereas the first circuit presents a time-varying input resistance level to the source. If the voltage source is not an ideal one,* i.e.,* if it has a non-zero internal resistance, the time constant of circuit in Fig. 11.3-11 (a) will change and hence the shape of its step response will change. However, the shape of step response will not change in the case of circuit Fig. 11.3-11 (b); but the final magnitude will change due to change in the ratio (*R*_{2}/*R*_{1}).

#### 11.3.5 Zero-State Response of Parallel *RC* Circuit for Sinusoidal Input

The zero-state response for sinusoidal input for any linear time-invariant circuit can be obtained in three ways.

- Let the input be sin
*ωt**u*(*t*). Obtain the zero-state response of the circuit for a complex exponential input function*e*, where^{st}*s*is a complex number. Substitute*s*=*jω*in the solution and accept the*imaginary part of the solution*as the zero-state response for sin*ωt u*(*t*) . - Express sin (
*ωt*) as [(*e*–^{jωt}*e*)/2^{– jωt}*j*] by using Euler’s formula, get the zero-state responses for the two exponential functions separately and use superposition principle. - Use phasor method to obtain the sinusoidal steady-state response and add a transient response term such that the total response satisfies initial conditions. Initial conditions will be zero valued since we are dealing with zero-state response.

The first two methods were already illustrated in the context of sinusoidal response of* RL *circuits in Chapter 10. We use the third method here to obtain the zero-state response for the voltage appearing across a Parallel* RC* Circuit excited by a sinusoidal current source with source function of sin *ωt* *u*(*t*) A.

The circuit in time-domain and phasor-domain are shown in of Fig. 11.3-12 (a) and (b), respectively.

**Fig. 11.3-12** Parallel *RC* circuit with sinusoidal excitation and its phasor equivalent

Going back to time-domain, we get the steady-state component of voltage across the Parallel* RC *Circuit as

Now we add a transient component of known form* Ae ^{– t / τ}* and evaluate

*A*such that the total solution is zero at

*t*= 0

^{+}. We get,

Since tan^{–l }*k* lies in first quadrant , sin(tan^{–1} *k*)

We normalise the time variable using the circuit time constant as the base and the output voltage by using the value of* R* as the base value and obtain the following expression for normalised voltage *v*_{on}(*t*) as a function of normalised time* t _{n}.*

This waveform for a case with* k* = 4 is shown in Fig. 11.3-13. We had noted under a similar context (Section 10.8 in Chapter 10 on* RL* Circuits) that the number* k* can be interpreted as a comparison between the characteristic time,* i.e.,* the period of the applied input and the characteristic time of the circuit,* i.e.,* its time constant.* k* can be expressed as 2*π*(*τ*/*T*), where* T *is the period of input. The value of* T* is indicative of the rate of change involved inthe waveform,* i.e.,* the* speed* of the waveform and time-constant is a measure of inertia in the system. Therefore, an input sinusoid is too fast for a circuit to follow, if its* T* is smaller than the time constant* τ* of the circuit. Similarly, if input sinusoid has a* T *value much larger than time constant of the circuit, the circuit will perceive it as a very slow waveform and will respond almost the same way it does to DC input. These aspects are clearly brought out in the expression in Eqn. 11.3-2.

**Fig. 11.3-13** Unit sinusoidal response (normalised) of a parallel *RC* circuit with *k* = 4

We make the following observations on the sinusoidal steady-state response of Parallel* RC* Circuit with* current source excitation* from Eqn. 11.3-2:

- The circuit voltage under sinusoidal steady-state response is a sinusoid at the same angular frequency
*ω*rad/s as that of input current sinusoid. - The circuit voltage initially is a mixture of an exponentially decaying unidirectional transient component along with the steady-state sinusoidal component. This unidirectional transient imparts an offset to the circuit voltage during the initial period.
- The circuit voltage at its first peak can go close to twice its steady-state amplitude in the case of circuits with
*ω**τ*>> 1 due to this offset. - The amplitude of sinusoidal steady-state response is always less than the corresponding amplitude when DC input is applied. This is due to the capacitive inertia of the circuit. When input is a current, capacitor in a circuit behaves as electrical inertia, and, when input is a voltage, inductance in a circuit behaves as electrical inertia. The amplitude depends on the product
*ω*and decreases monotonically with the*τ**ω*product for fixed input amplitude.*τ* - The response sinusoid (circuit voltage)
*lags*behind the input sinusoid (applied current) under steady-state conditions by a phase angle that increases monotonically with the product*ω**τ*. - The frequency at which the circuit gain becomes 1/√2 times that of DC gain is termed as
*cut-off frequency*and since this takes place as we go up in frequency it is called*upper cut-off frequency.*Upper cut-off frequency of Parallel*RC*Circuit is at*ω*= 1/*τ*rad/s. The phase at this frequency will be – 45°. - Circuit voltage amplitude becomes very small at high frequencies (
*ω**τ*>> 1) and the voltage lags the input current by ≈ 90° at such frequencies.

##### 11.4 PERIODIC STEADY-STATE IN A SERIES *RC* CIRCUIT

We address the issue of finding the zero-state response to* repetitive input* in* RC* circuits in this section and consider a specific example for doing so. Refer to Fig. 11.4-1.

**Fig. 11.4-1** Series *RC* circuit with repetitive square wave input

A symmetric square wave voltage with 1 V amplitude is applied from* t* = 0 to an initially relaxed Series* RC* Circuit. The period of the square wave is assumed to be equal to the time constant and the time scale is marked in terms of *t*/*τ*.

A step response starts at* t =* 0 and takes the output to (1 – *e*^{–0.5}) = 0.3935 V at *t*/*τ =* 0.5. Another zero-state step response starts in the negative direction at that point along with a zero-input response corresponding to an initial voltage of 0.3935V on the capacitor. Thus the output waveform can be expressed as = 0.3935 *e*^{–(t–0.5τ)/τ} – (1 – *e*^{–(t–0.5τ)/τ}) for the time range 0.5 ≤ *t*/*τ* ≤ 1. This expression may be evaluated at *t*/*τ **=* 1 to get the initial condition at that point and a new expression valid for 1 ≤ *t*/*τ* ≤ 1.5 may be obtained as a superposition of zero-input response and a new zero-state step response. This way the solution may be taken forward.

It may be observed that the values of capacitor voltage at the beginning and at the end of a cycle are not the same in the first few cycles of operation. However, after a few cycles, the circuit settles down to a mode of operation in which the output starts out with a particular value at the beginning of the cycle and returns to the same value at the end of that cycle only to repeat that process again in the next cycle. This means that the output too reaches a* repetitive* pattern after a few initial cycles. When the circuit reaches this kind of* repetitive* operation under the influence of any* repetitive* input, it is said to have reached a* periodic steady-state* with respect to that input. Figure. 11.4-1 shows that the capacitor voltage oscillates between 0.245 V and –0.245 V under periodic steady-state in the present instance, where* T* – the period of input – has been taken to be equal to *τ*, the time constant of the circuit.

It is not necessary to start at the beginning and march forward till the circuit reaches the periodic steady-state in order to find out the amplitude under steady-state condition. We can proceed in the following manner to develop an expression for this amplitude.

Let –*V*_{1} and +*V*_{2} be the negative and positive amplitudes in a cycle as shown in Fig. 11.4-1. Then the circuit would have reached steady-state when the output value at the end of the cycle turns out to be exactly –*V*_{1}.

with* t* measured from the beginning of cycle after the circuit has reached periodic steady-state

This expression evaluated with *t = T* should be equal to –*V*_{1} under periodic steady-state.

Substituting for *V*_{2} in terms of* V*_{1} and solving for* V*_{1}, we get ,

This expression evaluated with* T*/*τ *= 1 gives *V*_{1} = *V*_{2} = 0.245 V for a 1 V amplitude square wave input.

The key to the above derivation was our knowledge of step response of Series* RC* Circuit. The input could be thought of as a sequence of unit steps and hence the output could be strung together employing step response and zero-input response segments. Square waves and more generalised versions of it (the so-called* rectangular pulse waveforms* that are ‘squarish’ waveforms with unequal half-cycle duration and unequal positive and negative amplitudes) appear very frequently in Pulse Electronics Applications and Digital Electronics. And, Series* RC* Circuits are routinely used to model the transmission channel that takes such signals from one location to another location in the electronic system. Hence periodic steady-state of Series* RC* Circuit under rectangular pulse waveforms is of crucial significance in Analog and Digital Electronics. This is the motivation behind this section on periodic steady-state.

The method described above for finding out steady-state amplitudes under repetitive excitation will work only if we can identify the repetitive waveform as a sequence of some well-known shape like a step or ramp or sinusoid. However, in practice, we will be called upon to solve for periodic steady-state even when the period of input is of a complex shape. How do we proceed? The answer lies in *frequency response function H*(*jω*) of the circuit.

##### 11.5 FREQUENCY RESPONSE OF FIRST ORDER *RC* CIRCUITS

The concept of* sinusoidal steady-state frequency response* was already introduced in Chapters 9 and 10. Essentially, we apply a sinusoidal input of suitable amplitude to a circuit and wait for enough time for the transient response to die down. After steady-state is satisfactorily established in the circuit, we measure the amplitude of output and its phase with respect to the input sine wave. We repeat this process for various values of frequency of input. We ensure that the circuit is in steady-state before we measure the output every time. The data so obtained are plotted to show the variation of ratio of output amplitude to input amplitude and phase of steady-state voltage against* k* (=*ωτ*). Such a pair of plots will constitute what is called the* AC steady-state frequency response plots* for this circuit. The ratio of output amplitude to input amplitude is called the* gain* of the circuit. Its dimension will depend on the nature of input and the output quantities.

The same data can be obtained from the analytical model of the circuit if such a model exists. Consider the Series* RC* Circuit and its phasor model shown in Fig. 11.5-1.

**Fig. 11.5-1** Series *RC* circuit and its phasor model

Frequency response function,

The Gain and Phase plots for the circuit are shown in Fig. 11.5-2. The gain goes to 70.7% level at* ω* = 1*/**τ* rad/s and phase delay at that frequency is 45°.

**Fig. 11.5-2** Frequency response plots for series *RC* circuit

#### 11.5.1 The Use of Frequency Response

Frequency response information helps us to find the* steady-state output* when the input is a* mixture of sinusoids of different frequencies.* A sinusoid with a particular angular frequency is a periodic waveform. But a sum of many sinusoids with arbitrary frequencies need not be periodic. A special case is where the sinusoids in the additive mixture are of frequencies which are related* harmonically -i.e.,* when all the frequencies are integer multiples of some basic frequency value. This is an important practical case.

We have seen in Chapter 9 that a periodic non-sinusoidal waveform can be expanded as a sum of a DC component (which may be zero as a special case) and infinitely many sinusoids (may be finite as a special case) with harmonically related frequencies. Therefore, the periodic steady-state solution in a circuit excited by a non-sinusoidal periodic input can be obtained by using the Fourier Series of the waveform along with the frequency response data for the circuit. That makes frequency response an extremely important mathematical description of a linear circuit.

Before we proceed to employ frequency response to solve circuits excited by sum of sinusoids, let us settle an issue regarding superposition principle. We know that zero-state responses due to multiple sources acting simultaneously can be obtained by superposition. But does it work for steady-state response component too?

Zero-state response contains two components – the transient response part and the steady-state response part. The transient response components, whether from zero-state response or zero-input response, will vanish with time if the circuit is passive and stable. Therefore, superposition principle can be applied on steady-state response components.

Now, if the input contains many sinusoids with different frequencies, the steady-state response component due to each sinusoid may be obtained from frequency response plots and these components may be added up to obtain the complete steady-state response. This procedure is illustrated in the case of a Series* RC* Circuit with a time constant of 1 s and with an input of *v*_{S}(*t*) = (sin* t +* 0.33 sin 3*t* + 0.2 sin 5*t*) *u*(*t*) V. The output is taken across the capacitor.

Consider the first sinusoid that has an angular frequency of 1 rad/s. The gain of the circuit at this frequency is 0.707 and the phase delay is 45° (0.79 rad) (either from Eqn. 11.5-1 or from Fig. 11.5-2 with *τ* = 1 s). Therefore, the steady-state component due to this sinusoid is 0.707 sin(*t* – 0.79) V. The sond sinusoid of 0.33 sin3*t* with an angular frequency of 3 rad/s meets with a gain of 0.3162 and phase delay of 71.57° (1.25 rad). Therefore the steady-state component due to this sinusoid is 0.104 sin(3*t* – 1.25) V. Similarly, the third sinusoid of 0.2 sin 5*t* with an angular frequency of 5 rad/s meets with a gain of 0.1961 and phase delay of 78.7° (1.37 rad). Therefore, the steady-state component due to this sinusoid is 0.04 sin(5*t *– 1.37) V*.* Therefore, *v*_{o}(*t*) = 0.707 sin(*t *– 0.79) + 0.104 sin(3*t* – 1.25) + 0.04 sin(5*t* – 1.37) V. The input and output waveforms are shown in Fig. 11.5-3.

**Fig. 11.5-3** Steady-state response of series *RC* circuit for mixed sinusoidal input

#### 11.5.2 Frequency Response and Linear Distortion

We observe that our Series* RC* Circuit has meted out differential treatment to various sinusoids in the input mixture. It has shown a clear preference to the sinusoid with lowest frequency (with 1 rad/s) and passed it on with only about 30% loss of amplitude whereas the remaining two sinusoids with 3 rad/s and 5 rad/s frequencies suffered 68.5% and 80% loss of amplitude, respectively. Circuits that preferentially pass low frequency sinusoids to the output and curtail high frequency sinusoids are called* low-pass filters.* Low-pass filters will have a frequency response with a gain function that tapers down to zero as frequency goes up. Thus a Series* RC* Circuit with the output taken across the capacitor is a first-order low-pass filter. It shows a tendency to remove high frequency components in the input.

Further, we observe from Fig. 11.5-3 that the waveshape of output voltage is considerably different from that of input. This is inevitable in a filtering context. After all, some frequency components get removed or attenuated considerably in a filtering process and therefore the output cannot but look different compared to input! When the waveshape of output under steady-state in a circuit is different from the waveshape of input, the circuit is said to have* distorted* the signal. Thus,* distortion* invariably follows* filtering.* When the change in waveshape is the desired outcome, we call it* filtering*; when the change in waveshape is the undesired outcome we call it* distortion.*

This distortion of waveshape arises out of two reasons. Sinusoids at different frequencies meet with different gains in the circuit and therefore the mix of amplitudes,* i.e.,* the relative ratio of amplitudes of various sinusoids, will be different at output and input. In the example we considered, the ratio was 1:0.33:0.2 at input and 1:0.147:0.057 at the output. Waveshape changes due to this change in amplitude mix. Distortion arising out of this mechanism is called* amplitude distortion* and it is due to the gain response part of frequency response.

The second cause of distortion comes from phase response. Each sinusoid suffers a time delay when it goes through the circuit – the time delay is measured between zero crossing of that sinusoid in the input and in the output. Phase delay is equal to time delay multiplied by angular frequency. Thus the 1 rad/s component in the previous example underwent a delay of 0.79 s, the 3 rad/s component suffered a delay of 1.25 rad/ 3 rad/s = 0.42 s and the 5 rad/s component was subjected to a delay of 1.79 rad/5 rad/s = 0.36 s.

**Fig. 11.5-4** Illustrating phase distortion due to dispersion

All the three cross the time-axis simultaneously at the input. But at the output they do not cross the time-axis simultaneously – the 5 rad/s crosses first followed by the 3 rad/s component and the 1 rad/s component is the last one to cross the time-axis. Thus, they get* dispersed.* This* dispersion* results in change in waveshape. Refer to Fig. 11.5-4. The three components in the input are shown in Fig. 11.5-4 (a) and the corresponding components in the output are shown in Fig. 11.5-4 (b). The dispersion in zero-crossing instants is clearly brought out in Fig. 11.5-4 (b). The distortion resulting from dispersion of components brought about by* unequal time delays* suffered in going through the circuit is termed as* phase distortion.* Of course, in any distortion context these two – amplitude distortion and phase distortion – are mixed up and cannot be separated out.

*Phase distortion* arises essentially due to phase response part of frequency response. If all the sinusoids are delayed by* same time delay* there will be no change in waveshape (assuming there is no amplitude distortion). The entire input waveshape will get bodily shifted in time-axis by a definite delay and will appear as output in that case. Therefore, either zero time delay for all frequencies or constant time delay for all frequencies will prevent phase distortion. A constant time delay implies that the phase delay must be a* linear function of ω*.

The conditions to be satisfied by a circuit such that there is no waveshape distortion when a signal passes through it must be evident now – its frequency response must have a gain that is flat with *ω* and a phase which is either zero or linear on *ω*,* i.e.,* of the form *ɸ** = –kω* where* k* is a real number.

Obviously only a memoryless circuit can satisfy this. Hence a circuit which contains at least one inductor or capacitor will cause waveshape distortion in general. Similarly, we conclude that a memoryless circuit cannot function as a* filter*; we will need inductors and capacitors for that.

We observe that, in the example we analysed in this section, the input contained three sinusoids of 1 rad/s, 3 rad/s and 5 rad/s and the output contained exactly three sinusoidal components with the same frequencies as in the input. In short, the circuit did not change the frequency of sinusoids. Neither did it generate a sinusoid with a frequency that was not there in the input. This, in fact, is a property of any lumped linear time-invariant (LLTI) system. They can only scale, differentiate or integrate signals. And these three mathematical operations cannot produce a sinusoid with a frequency that is different from that of input.

Therefore, a single frequency sinusoid cannot suffer waveshape distortion in passing through a linear time-invariant circuit.

However, a non-linear circuit can change the waveshape of a single frequency sinusoid. Apply about 10mV of 1kHz sinusoidal voltage to a 741 Operational Amplifier non-inverting pin after grounding the inverting pin. The Operational Amplifier is in the open loop and its large gain results in output getting saturated. We will observe a waveform that is almost a square wave at the output. That is* non-linear distortion.* The waveshape distortion we observed in the example in this stion was not due to non-linearity. It occurred due to differential treatment experienced by various sinusoidal components in a mixture of sinusoids when they went through the circuit. The distortion which occurs due to frequency response of a linear circuit is termed as* linear distortion* in order to distinguish this kind of distortion from distortion due to non-linearity.* Amplitude Distortion* and* Phase Distortion* are the two inseparable components of* Linear Distortion.*

One should not be under the impression that the Series* RC* Circuit can function only as a low-pass filter. In fact, the kind of filter realised by a given circuit will strongly depend on where exactly is the input applied and where exactly is the output taken. A Series* RC* Circuit excited by a voltage source at the input with output taken across the capacitor is a low-pass filter. The same circuit with the same excitation but with the output taken across the resistor is a high-pass filter that passes the high frequency sinusoids to the output and curtails the low frequency components including DC.

#### 11.5.3 First-Order *RC* Circuits as Averaging Circuits

A Series* RC* Circuit with voltage excitation and output taken across the capacitor is a low-pass filter. Similarly, a Parallel* RC* Circuit with current excitation and output taken across the parallel combination is also a low-pass filter.

*Averaging* is a signal processing application that appears often in analog and digital signal processing. The waveform to be averaged is typically a rectangular pulse waveform with a slowly varying DC content. An* averaging circuit* produces an output that is the DC content of input signal.

Consider the rectangular pulse waveform shown in Fig. 11.5-5. It has an amplitude of 1 V, a frequency of 1kHz and a duty ratio of 0.2. This waveform can be thought of as the sum of a DC voltage of value 0.2 V and a pure alternating waveform with zero full-cycle area (*i.e.,* zero DC content). These two components are also shown in Fig. 11.5-5.

**Fig. 11.5-5** A rectangular pulse waveform and its components

Assume that this waveform is applied to a Series* RC* Circuit with* R =* 10 kΩ and* C =* 1*μ*F from* t* = 0 . The time constant is 10 ms. Output is taken across the capacitor. The total zero-state response can be obtained by using superposition principle. Therefore, we expect the standard step response scaled by 0.2 to be present along with other components in the output. This step response component will reach steady-state in about 5*τ*,* i.e.,* in 50ms and contribute 0.2 V steady component to the output after that.

The pure alternating component of applied voltage also will reach a periodic steady-state at the output after about 50ms. We remember that this alternating component can be thought of as the sum of infinitely many sinusoids of frequencies that are integer multiples of 1kHz. The lowest frequency component will be 1kHz. The phasor impedance of capacitor and the resistor share the sinusoidal voltage under steady-state and we are interested in the voltage absorbed by the capacitor. Let us calculate the phasor impedance of capacitor at 1kHz. It is –*j*159.2 Ω. We see that this is only about 1.6% of the resistor value (10 kΩ) and hence we expect the capacitor to absorb only a very small percentage of sinusoidal voltage at 1kHz – most of it will appear across the resistor. This will be more so for other sinusoidal components with frequencies higher than 1kHz since phasor impedance of capacitor goes down with frequency.

As a first approximation, we assume that the alternating component that appears across capacitor is negligible when we calculate the alternating component of current in the circuit. Thus, the alternating component of applied voltage is assumed to appear across 10kΩ almost entirely, thereby resulting in a current whose waveshape will be the same as that of alternating component of voltage. This current will vary between 0.08 mA and –0.02 mA. Now we work out the small voltage that appears across capacitor due to this alternating current flow.

The half-cycle area of this current is 0.08 mA × 0.2 ms (or 0.02mA × 0.8 ms) = 0.016* μ*C*.* Hence, the peak-to-peak voltage across the capacitor due to the alternating current flow will be 0.016 *μ*C/ 1 *μ*F = 0.016 V*.* Hence the total capacitor voltage will vary in the range 0.2 ± 0.008 V*.* The variation is ± 4% of the desired average value of 0.2 V*.*

This approximate solution is confirmed by the accurate solution worked out using the method to solve for periodic steady-state explained earlier in this stion. This is shown in Fig. 11.5-6. The output waveform segments are actually exponential; but they appear nearly straight-line segments confirming the validity of assumption employed in our approximate reasoning.

**Fig. 11.5-6** Input and output waveforms of series *RC* averaging circuit

*We should not ever forget that a circuit reaches steady-state only after covering the transient period. *This reasonably clean average value appears only after 50 ms of applying the input. We can increase the time constant of the circuit to higher levels in order to make the output appear cleaner; but there is a price to pay.* The cleaner output will take longer to establish.* The average value of input is not likely to remain constant forever in a practical application of averaging circuit. In fact, this value may be used to code some information and will consequently change slowly. Typically, the duty ratio of the input wave changes slowly while its frequency is kept constant. And the averaging circuit is expected to track the change in average value faithfully. Obviously there is a conflict between the requirement of a clean output and the requirement of a fast response to changing DC content at input. The time constant of the circuit must be selected in such a way that it has enough speed to catch up with the average value variation. And, if the ripple in the output is excessive with that value of time constant, we better look for some other better technique to do averaging!

Parallel* RC* Circuit can be employed for averaging current signals subject to similar constraints. Essentially,* averaging* is only a special case of low-pass filtering. Good averaging performance requires that* τ* >>* T,* where* T* is the period of the input signal or its characteristic time of variation if a regular period cannot be identified.

#### 11.5.4 Capacitor as a Signal Coupling Element

Another application context involving the Series* RC* Circuit is the ‘*signal coupling problem*’ in electronic amplifiers. We abstract the problem as follows.

At a certain input point in the electronic amplifier a certain value of DC voltage has to be established using a DC source and resistors. This DC voltage is needed to fix the operating point of transistors in the amplifier at suitable levels. Yet, we want to connect an AC signal source to that input point without upsetting the DC potential there. Interposing a suitably sized capacitor between the signal source and input point achieves this objective. The capacitor used for this purpose is called* coupling capacitor *and amplifiers employing this form of signal coupling are called* RC-Coupled Amplifiers* in the study of Electronic Circuits. Notice that the* RC* circuit is used as a* high-pass filter* (or* average absorber*) in this application.

This application is explained further in the following example.

Consider the signal-coupling problem presented in Fig. 11.5-7. The signal *v*_{S}(*t*) is a mixture of sinusoids and may contain sinusoids of frequency from 20 Hz to 20 kHz (the standard audio range). It is desired that 95% of signal amplitude appear at the point A for the entire frequency range without affecting the DC content of voltage at that point. (i) Calculate the value of* C* needed for this purpose. (ii) Assume *v*_{S}(*t*) is a 500 mV amplitude 20 Hz sine wave and plot the potential at A and the voltage across the coupling capacitor with the value of* C* calculated.

**Fig. 11.5-7** Circuits for *RC* signal-coupling example

**Solution**

Consider the circuit in Fig. 11.5-7 (a). The 100kΩ resistor produces only negligible loading at the point A and hence the current drawn by it may be ignored. Then the DC voltage at that point is 12 V × (2/10+2) = 2 V with respect to the negative of DC source.

Now if the AC signal source is connected straight at point A as in Fig. 11.5-7 (b) the DC voltage at that point gets affected. In fact it goes to zero if *v*_{S}(*t*) has no DC content. This is a two-source problem and can be solved by applying superposition principle. When the DC source alone is considered, the AC source has to be shorted (assuming it is an ideal independent voltage source). This short will reduce the DC potential at point A to zero once the signal source is connected. Hence direct coupling will not work.

The circuit Fig. 11.5-7 (c) is also excited by two sources. We know that the steady-state responses due to many sources obey superposition principle in a linear time-invariant circuit. The two equivalent circuits needed for calculating the steady-state response are shown in Fig. 11.5-8.

**Fig. 11.5-8** Circuits for applying superposition in Example: 11.5-1

The DC component of a steady-state response at point A is 2 V (neglecting the effect of 100kΩ resistor) since a capacitor behaves as an open-circuit under DC steady-state, and the DC content in *v*_{C}(*t*) is also 2 V

As far as steady-state component of AC signal is concerned, we want 95% of input amplitude to appear at point A even at 20 Hz. The parallel combination of the three resistors is 1.64 kΩ . The signal voltage gets divided between the phasor impedance of capacitor, 1*/*(*j*2*π *× 20C), and 1.64 kΩ .

We desire this to be ≥ 95%.

Therefore the capacitance value required is 14.8 *μ*F

The ratio between voltage at A to voltage at input at 20 Hz has a gain value of 0.95.

Therefore with 500 mV amplitude sine wave at input there will be a steady-state component of (500 × 0.95 mV) sin (40*π** t +* 0.317) at point A.

Therefore total steady-state voltage at A = 2 + 0.475 sin (40*π** t +* 0.317) V

**Fig. 11.5-9** Waveform plots for Example: 11.5-1

#### 11.5.5 Parallel *RC* Circuit for Signal Bypassing

The need for making a resistor offer its full resistance to DC current flow and near-zero resistance to signal (*i.e.,* alternating component) current flow arises often in Electronic Circuit applications. Constructing a Parallel* RC* Circuit by adding a capacitor in parallel to the concerned resistor is the standard solution to this ‘*signal bypassing*’ problem. The capacitor is sized suitably such that it offers a phasor impedance with very small magnitude compared to the resistance value of the resistor to be bypassed even for the lowest frequency sinusoidal component that is present in the signal current.

Parallel* RC* Circuit is used as a low-pass filter with its bandwidth much lower than the lowest frequency present in the signal in* signal bypassing* application.

The DC component of total current flowing into the parallel combination goes through the resistor under steady-state. But all the AC components flow almost entirely through the capacitor since it offers much lower impedance than the parallel resistor at the frequencies concerned. The voltage across the combination remains nearly DC. The next example illustrates this application of a Parallel* RC* Circuit.

**Example: 11.5-2**

Consider the ‘*signal bypassing*’ context in Fig. 11.5-10. The signal *v*_{S}(*t*) is a mixture of sinusoids and may contain sinusoids of frequency from 20 Hz to 20 kHz (the standard audio range). The coupling capacitor* C*_{1 }may be assumed to be so large that it is effectively a short-circuit at all frequencies except at DC. It is desired that more than 95% of applied signal voltage appear across the 1 kΩ resistor for the entire frequency range without affecting the DC content of current through that resistor. (i) Calculate the value of* C* needed for this purpose. (ii) Assume *v*_{S}(*t*) is a 10 mV amplitude 20 Hz sine wave and plot the waveforms of total current through 1 kΩ , 99kΩ and the capacitor with the value of* C* calculated above.

**Fig. 11.5-10** Circuit for signal bypassing problem in Example: 11.5-2

**Solution**

The equivalent circuits needed for calculating the steady-state response contributions from the DC source and signal source are shown in of Fig. 11.5-11 (a) and (b), respectively.

**Fig. 11.5-11** Steady-state equivalent circuits in Example: 11.5-2

Solving the circuit in Fig. 11.5-11 (a), we get the DC potential at the point A as 1.97 V, the DC current through 1 kΩ and 99 kΩ resistors as 0.0197 mA and the DC potential across 99 kΩ resistor (and hence across the capacitor C_{2}) as 1.95 V

Consider the circuit in of Fig. 11.5-11 (b). We desire the amplitude of signal voltage across 1 kΩ to be ≥ 95% of amplitude of applied signal voltage even when the signal is a 20 Hz sinusoid.

Ratio of phasor voltage across 1kΩ to applied phasor voltage

We want the magnitude of this ratio to be 0.95. Solving for C_{2} we get C_{2} = 24.5 *μ*F.

Substituting this value of C_{2} in the phasor ratio above, we get the ratio as 0.95*∠*0.32 rad.

Almost the entire signal current flowing through 1 kΩ resistor goes into the capacitor. Thus the 99 kΩ resistor has been bypassed very effectively by a 24.5 *μ*F even at 20 Hz. The relevant waveforms are shown in Fig. 11.5-12. Voltages shown are with respect to the negative terminal of the DC source.

**Fig. 11.5-12** Waveforms for Example: 11.5-2 (a) Total current in 1kω resistor (b) Total current in the capacitor (c) Total current in 99kΩ resistor (d) Total voltage at A (e) Total voltage across capacitor

##### 11.6 SUMMARY

- Series and parallel
*RC*circuits are described by a first-order linear differential equation. The past history of the circuit is contained in a single initial condition specification for capacitor voltage in*RC*circuits. - The solution of the differential equation describing the capacitor voltage in an
*RC*circuit contains two terms – the complementary function and particular integral. Complementary function is the solution of differential equation with zero-forcing function. Particular integral is the solution of the differential equation*due to input function.*The total solution is obtained by adding these two. The complementary function has arbitrary amplitude that should be fixed by ensuring that the*total*solution complies with the specified initial condition. - The circuit variables in the
*RC*circuit will contain two response components –*transient response*(also called*natural response*) and*forced response. Natural response*is the way in which the inertia in the circuit reacts to forcing function’s command to change. Complementary solution gives the*natural response*and particular integral gives the*forced response*in a circuit. - The
*natural response*of a circuit is independent of the type or magnitude of forcing function and depends only on circuit parameters and the nature of interconnections.*Natural response*in*RC*circuit is exponential of the form*A e*where^{-t/τ},*τ = RC*is defined as time constant of the circuit.*A*is to be fixed by complying with initial condition. - The initial capacitor voltage in an
*RC*circuit at*t*= 0^{–}and*t*= 0^{+}are the same if the circuit does not contain impulse sources. - In the case of
*RC*circuit,*step response*is a rising exponential, approaching a steady-state value asymptotically as*t*→ ∞. The*step response*never gets done. But for practical purposes it may be considered to be over within 5 time constants. *Free-response*of an*RC*circuit is its response when input is zero and there is some initial energy trapped in the capacitor. It will contain only*natural response*terms. The capacitor voltage in this case falls exponentially towards zero.- The response due to initial energy and application of impulse are indistinguishable in an
*RC*circuit and hence they can be replaced for each other. An initial voltage of*V*in a capacitor of value_{0}*C*can be replaced by zero initial condition with a current source*CV*_{0}*δ*(*t*) connected*in parallel with*the capacitor. *Step response*and*ramp response*in a*RC*circuit can be obtained by integrating its*impulse response*successively.- Waveshape distortion occurs in linear circuits due to differential treatment experienced by various sinusoidal components in a mixture of sinusoids when they go through the circuit. The conditions to be satisfied by a circuit such that there is no waveshape distortion when a signal passes through it, is that its frequency response must have a gain that is flat with
*ω*and a phase which is either zero or linear on*ω*, i.e., of the form*ɸ*=*–kω,*where*k*is a real number. - A Series
*RC*Circuit excited by a voltage source at the input of the series combination with output taken across the capacitor is a low-pass filter with a cut-off frequency of 1*/**τ*rad/s and a monotonically decreasing gain. The same circuit with same excitation but with output taken across the resistor is a high-pass filter with a cut-off frequency of 1*/**τ*rad/s and a monotonically increasing gain. - Series
*RC*circuit with output taken across capacitor can be used as averaging filter for voltage signals and parallel*RC*circuit with output taken across the combination can be used as averaging filter for current signals. Good averaging performance requires that*τ*>> T, where*T*is the period of the input signal or its characteristic time of variation if a regular period cannot be identified.

##### 11.7 PROBLEMS

[Circuits are initially relaxed unless specified otherwise]

- What is the differential equation describing
*v*_{C}(*t*) for*t*≥ 0^{+}in the circuit in Fig. 11.7-1?**Fig. 11.7-1** - A parallel
*RC*circuit with non-zero initial energy is driven by a 1A DC current source from*t*= 0.*v*_{C}(*t*) is found to reach 75% of its steady-state value in one time constant. Express the initial voltage across capacitor as a percentage of its steady-state value. - A parallel
*RC*circuit is driven by a 1A DC current source from*t*=0.*v*(_{C}*t*) is found to be 50% at*t*=*τ*. Was there any initial voltage across C? If so, what is its magnitude and polarity? - Find and plot the v
_{C}(*t*) and voltage across the current source as functions of time in Fig. 11.7-2. Is there any exponential function in the expression for*v*_{C}(*t*)? If not why?**Fig. 11.7-2** - Derive an expression for
*v*_{C}in an initially relaxed series*RC*circuit when it is driven by*v*_{S}(*t*) =*t*for 0^{+}≤*t*≤*τ*and 0 for all other*t*, where*τ*=*RC*t. - What is the time required for the energy stored in
*C*in a series*RC*circuit with voltage source input to reach 99% of its steady-state value in step response? *v*_{C}in the circuit in Fig. 11.7-3 is –10 V at*t*= 0^{–}. If*v*_{C}(*t*) = 0 for*t*≥ 0^{+}, find C.**Fig. 11.7-3**- A parallel
*RC*circuit is driven by a 1A DC current source from*t*= 0. The resistor voltage is found to be (10 – 5e^{–t}) V for*t*≤ 0^{+}. What are the values of*C*,*R*and initial voltage? *v*_{C}in the circuit in Fig. 11.7-4 at*t*= 0^{–}is –12 V*.*It is found that*v*_{C}(*t*) = 0 for*t*≤ 0^{+}. What is the rise time of step response of the circuit?**Fig. 11.7-4**- A parallel
*RC*circuit with non-zero initial energy is driven by a 1A DC current source from*t*=0. The capacitor voltage is found to be 15 V for*t*≤ 0^{+}. What is the value of initial voltage and what is its polarity relative to the observed voltage? What is the value of*R*in the circuit? - A parallel
*RC*circuit with non-zero initial energy is driven by a 1A DC current source from*t*=0. The resistor current is found to be 12 mA under steady-state. What is the new steady-state value of this current if (i) the initial condition is doubled (ii) if 2*u*(*t*) is applied with no change in initial condition? - The capacitor voltage
*v*_{C}(*t*) = 0 for*t*≤ 0+ in the circuit in Fig. 11.7-5. Find the values of*V*_{0}and*I*_{S}. The circuit elements that produced initial energy storage in the capacitor are not shown.**Fig. 11.7-5** - A series
*RC*circuit with zero initial current is driven by*v*_{S}(*t*) =*δ*(*t*) –*δ*(*t*–1). Its time constant is 1 s. (i) Starting from impulse response, find the voltage across the resistor in the circuit when driven by the input*v*(_{S}*t*)*.*(ii) Using the result derive an expression for voltage across the resistor when the circuit is driven by a rectangular pulse of unit amplitude and 1 s duration. - Derive expressions for maximum voltage across resistor in an initially relaxed series
*RC*circuit when it is driven by*e*(^{αt}u*t*) A with*α*≠ –1/*τ*, where*τ*is the time constant of the circuit. Also find an expression for the time instant at which this maximum voltage occurs. - An input of
*k**δ*(*t*) + 2e^{–2 t/τ }V is applied to an initially relaxed series*RC*circuit with time constant of*τ*s. The output across capacitor for*t*≤ 0^{+}is observed to contain only e^{–2 t /τ}waveshape. What is the value of*k*? - The desired voltage across a parallel
*RC*with initial condition as shown in the Fig. 11.7-6 is given by*v*(*t*) =2*t*for*t*≤ 0 and 0 for*t*< 0. Find the*i*_{S}(*t*) to be applied to the circuit if the initial condition is 5 V. Sketch the required*i*_{S}(*t*).**Fig. 11.7-6** - The switches in Fig. 11.7-7 are ideal. (i) Find the voltage across
*C*and plot it. (ii) Find the current through*C*and plot it. (iii) Find the voltage across the first resistor and plot it.**Fig. 11.7-7** - Initial voltage at
*t*= –∞ in the capacitor in the circuit in Fig. 11.7-8 was zero. Find the voltage across capacitor and current through it for*t*≤ 0^{+}and plot them.**Fig. 11.7-8** - The switch in the circuit in Fig. 11.7-9 was closed for a long time and is opened at t = 0. Find and plot the current in
*C*and voltage across*C*as functions of time.**Fig. 11.7-9** - Find the impulse response of the voltage variable
*v*(*t*) in the circuit in Fig. 11.7-10.**Fig. 11.7-10.** *v*_{C}(*t*) at 0 in the circuit in Fig. 11.7-11 is –*V*. The switch S is closed at*t*= 0. Show that*v*_{C}(*t*) will cross zero at*t*= 0.69RC s.**Fig. 11.7-11**- A pulse of height V V and width
*T*s is applied to a series*RC*circuit with zero initial condition as in Fig. 11.7-12 . (i) Plot the output for (a)*RC = T*(b)*RC =*10*T*and (c)*RC =*0.1*T*(ii) Find the relation between*RC*and*T*if the area of output pulse after*T*s is to be less than 10% of area of output pulse from 0 to*T*s.**Fig. 11.7-12** - What must be the value of
*k*in the circuit in Fig. 11.7-13, if*v*(*t*) = 0 for*t*≤ 0^{+}?**Fig. 11.7-13** - A single pulse defined as
*v*_{S}(*t*) = 10*t*for 0*≤ t*≤ 1 and 0 otherwise is applied to a series*RC*circuit with a time constant of 0.3 s. Find and plot the capacitor voltage. - Find the time constants for each circuit in Fig. 11.7-14 for voltage excitation and current excitation. All resistors are 1kΩ and all capacitors are 1
*μ*F.**Fig. 11.7-14** - The Inverter in the circuit in Fig. 11.7-15 is a digital electronic gate circuit and its input and output behaviour is as shown in the waveforms. Each inverter gate has 15pF input capacitance. The gate circuit will draw only zero current from +V supply if its input is held at V V or 0V steadily. The output of one such gate is connected as input to 4 such gates. Calculate (i) the power dissipation in the driving gate and (ii) the average power supply current drawn by the driving gate when the input to driving gate is a square wave varying between +V and 0 with a frequency
*f*for (a)*V =*5V,*f =*100kHz (b)*V =*5V f=10MHz (c)*V =*15V,*f =*100kHz (d)*V =*15V,*f =*10MHz.**Fig. 11.7-15** - A symmetric square wave of ±V amplitude and period of
*T*s is applied to a high pass*RC*circuit as shown in Fig. 11.7-16. After a few cycles of initial transient the output waveform settles to a periodic steady-state as shown where*V*_{1}*'*and V_{2}*'*will be equal to*V*_{1}and*V*_{2}, respectively, under periodic steady-state. The slanting portion of output wave will be exponential with time constant =*RC.*However, if*RC*>>*T*(equivalently, if the cut-off frequency of the circuit is much less than the square wave frequency) we can approximate the exponential by straight-line segments. Use this approximation and find expressions for*V*_{1}and*V*_{2}. Also find an expression for the so-called “percentage tilt” defined as 100 × (*V*_{1}–*V*_{2})/*V***Fig. 11.7-16** - Let
*V*_{s}(*t*) be an arbitrary time varying periodic voltage source with a cycle average value of*V*_{dc}. This means that*V*_{s}(t) can be written as*V*_{dc}+*V*_{ac}(*t*), where*V*_{ac}(*t*) is a time varying periodic component with equal positive half cycle and negative half cycle areas. Let that area be*A*V-s.

This waveform**Fig. 11.7-17***V*_{s}(*t*) is applied to a series*RC*circuit and output voltage is taken across C. Assume that*RC*>>*T*where*T*is the period of*V*_{s}(*t*) . Show that under periodic steady-state the (i) average value of output voltage is*V*_{dc}(ii) the peak-to-peak ripple in output voltage ≈*A*/*τ*V, where*τ*=*RC.*(iii) Calculate the quantities in (i) and (ii) for the three inputs given in Fig. 11.7-17, if*τ*is 20ms. (The Series*RC*Circuit can be used to extract average value of the input. The basic issue involved in this application is the tradeoff between ripple in the average value Vs response time) - The switch S
_{1}in Fig. 11.7-18 is closed at*t*= 0 with zero initial condition in the capacitor. The switch S_{2}is kept open for*T*_{1}s and closed for (*T*–*T*_{1}) s periodically. Obtain the voltage across capacitor and plot it assuming the following data.*V*= 12V,*R*= 12 kΩ,*C*=*1μ*F,*T*_{1}= 10ms,*T*= 11ms and Resistance of S_{2}when it is ON = 100 Ω.**Fig. 11.7-18** - The source-free response in an
*RC*circuit takes the capacitor voltage from 10 V to 3V in 20ms. What is the bandwidth of a low-pass*RC*filter made using the same components? - The steady-state voltage across resistor (
*v*_{R}) in a series*RC*circuit has an amplitude of 7.07V when the circuit is driven by an AC voltage of amplitude 10V and angular frequency*ω*rad/s. (i) Find the phase angle of*v*_{R}with respect to the input sinusoid. (ii) If another sinusoidal voltage of 15V amplitude and 3*ω*rad/s frequency is applied to the circuit, find the amplitude and phase of*v*_{R}under steady-state condition. - The bandwidth of a low-pass
*RC*filter is 2kHz. If a 10V DC source is applied to this series*RC*circuit (capacitor is uncharged before applying this source) at*t*= 107ms, find*t*at which the voltage across resistor will be 3 V. - A Series
*RC*circuit is excited by a sinusoidal voltage source at 3kHz. The voltage across the resistor is seen to lead the input voltage by 30°. If this*RC*circuit undergoes source-free response, how much time will it take to dissipate 50% of its initial stored energy in the resistance? - A Series
*RC*circuit is excited by a sinusoidal voltage source at 1kHz. The voltage across the capacitor is seen to lag the input voltage by 30°. What is the cyclic frequency of input sinusoid such that the voltage across the resistor will lead the input by 30°? - A Series
*RC*circuit is excited by a sinusoidal voltage source at 10kHz. The voltage across the capacitor is seen to be 50% of the input voltage in amplitude. What is the cyclic frequency of input sinusoid such that the voltage across the resistor will be 50% of the input voltage in amplitude? - A Series
*RC*circuit is excited by a sinusoidal voltage source at 100kHz. The voltage across the capacitor is seen to be 30% of the input voltage in amplitude. What is the cyclic frequency of input sinusoid such that the voltage across the resistor will lead the input voltage by 60°? - An AC voltage source =
*V*sin*ω*t is applied to a series*RC*circuit from*t*= 0. The circuit current is found to be = 0.7sin (*ωt*–*π/*3 )A for*t*≤ 0^{+}. Was there any initial voltage across the capacitor? If so, what is its magnitude and relative polarity? - The fall time of a series
*RC*circuit is 6.6 ms. If the same components are used to make a parallel*RC*circuit excited by a sinusoidal current source*i*_{S}(*t*) = 0.5 sin 300*πt*A, find the steady-state current in the resistor in the circuit. - A parallel
*RC*circuit has*C*= 10*μ*F. It is excited by an AC current source of 100mA amplitude and 5kHz frequency. The sinusoidal voltage across the combination is seen to lag the applied input by 60°. Find the value of*R*and the amplitude of voltage across the combination. - A current signal
*i*_{S}(*t*) = (2 sin*ωt*– 1.2 sin 3*ωt*+ 0.8 sin 5*ωt*)*u*(*t*) mA is applied to a parallel*RC*circuit of bandwidth 0.8*ω*. Find and plot the steady-state waveform of voltage across the circuit.