CHAPTER 12. Some PIC microcontroller advances
The world of embedded systems is one of relentless change. Higher speed, more flexibility, lower cost and lower power consumption are being demanded continuously. So far, we have picked up the fundamental techniques and technologies of embedded systems, using microcontrollers chosen because they demonstrate well the principles that we need to know about. There are of course any number of more sophisticated features which they do not carry. As we move to a more advanced level of study, it becomes useful to know about some of these features. That is the purpose of this chapter. It aims:
• To introduce in overview two microcontrollers which show some enhanced features, the 16F88 and the 16F883 – these can be viewed as upgrade paths for the microcontrollers used to date.
• To introduce some enhanced power management and oscillator techniques.
• To introduce some enhanced peripherals.
It is worth noting that in this chapter we appear to remain rooted in the world of the 16 Series. Many of the concepts and features introduced here are, however, used in the more advanced PIC microcontrollers, and in the world of embedded systems in general. You can read this chapter with a view to looking for upgrade paths, and/or to learn about developments that are available, to apply when you come to want them.
In general, the features introduced in this chapter are given in overview form only. The idea here is to give a taste of some things that are possible or available, rather than to give full design information. This may also accompany a shift in your own approach. In general, the beginner strives to know one or two microcontrollers well, and draws his/her confidence and understanding from that knowledge. But the embedded world is a complex and shifting place. Therefore the intermediate and advanced player in the field knows the principles well and has experience in using them, and applies these readily to each new microcontroller or system that he/she works on. There is less dependence on detailed knowledge of just one device. At this stage in the book, it is possible that you are moving to this outlook. Of course, for the full detail of a microcontroller, it remains essential to consult the data supplied by the manufacturer. Relevant data sheets are hence, as always, referenced at the end of the chapter.
12.1. The main idea – higher performance, more flexibility
Microcontrollers are wonderfully flexible things, but face inexorably opposing forces in their design. We want them small, cheap and of low power consumption, yet flexible, fast and functionally powerful. Small and low power consumption implies a limited number of IC pins and few features, but flexible and powerful seems to imply many pins and many features. As part of this chapter we see how Microchip squares up to these opposing forces, in answering the questions:
• Can we add flexibility by loading on more peripherals, and increasing their configuration options?
• At the same time, can we constrain the pin count by making pins more multi-functional?
• Can we reduce the overall system component count and hence free up pins by making more things completely `on-chip'?
• Can we conserve power, applying every trick possible with clock manipulation and selective power-down?
• Can we respond to specialist protocols and applications, for example in the world of networking or machine control?
• Can we still make a new microcontroller backward-compatible with devices it aims to replace?
12.2. The 16F87/88
In Chapter 2, Chapter 3, Chapter 4, Chapter 5 and Chapter 6 we used the 16F84A, a faithful PIC workhorse. One of its attractions is its comparatively small, 18-pin footprint. Yet the 16F84A is quite limited in what it can do. Can we keep with this scale of microcontroller, but add to what it can do? One answer lies with the 16F88, which we first met in Table 2.1, along with its kid brother, the ’F87. Let's see now what this microcontroller can do.
12.2.1. Architecture overview
Figure 12.1 and Figure 12.2 show the pin connection and block diagrams of the ’F88, taken from Reference 12.1. Carefully compare these two figure 2.1 and figure 2.2. In the architecture, the big difference is the block of peripherals that lie across the bottom of the ’F88 diagram. The EEPROM shown top right of Figure 12.2 is relegated to being one of these peripheral blocks in Figure 12.2. An alternative comparison to make is with the 16F873A structure, Figure 7.2. Almost all the peripherals seen in the larger ’F873A can also be seen in the ’F88; only Port C and one CCP are missing. It is worth noting that both the 16F873A and the 16F88 have two comparators and a voltage reference, even though Figure 7.2 seems to imply a single comparator, and Figure 12.2 does not show a voltage reference.
With all these extra peripherals, the mere 18 pins of the ’F88 are very busy indeed. It remains of course up to the programmer to decide which function a pin is actually used for. Notice, however, that in all the complexity of the ’F88, each connection of the ’F84A can be found in the same place. Aside from anything else, we have a chance therefore to use the ’F88 as a direct upgrade for the ’F84A in an existing design.
While the 16F88 has the same pin-count as the ’F84A, in many ways it appears more like a 16F873A. Table 2.1 shows that it has the same program memory size as the ’F873A. It comes as no surprise therefore that these two have the same program memory maps, i.e. Figure 7.4. With similar peripheral count, the data memory map of the ’F88 is similar to that of the ’F873A, i.e. Figure 7.6. Small changes are there of course, for example due to the larger data memory of the ’F88 and the fact that it needs SFRs for only two parallel ports. Direct Address, Indirect Address and RAM Address buses are also all of the same size, and larger than the ’F84A.
So is the 16F88 just the same as the ’F873A, squeezed into an 18-pin IC? To some extent the answer is `yes', but later in the chapter we find some important advances contained within it, relating mainly to the interconnected themes of power and clock management.
12.2.2. The 16F88 peripherals
With the 16F88 having more functions loaded onto each pin, there is an inevitable increase in the complexity of the pin driver circuits. In the familiar pattern, each parallel port retains a register for data transfer (PORTA, PORTB), and a register to define data direction (TRISA, TRISB). Now more or less every pin, however, has its own unique pin driver circuit, and the comparative simplicity of (for example) Figure 3.10 and Figure 3.11 is lost. Just one pin driver example is given here, for Port A pin 3, shown in Figure 12.3. It is interesting to observe the incremental increase in complexity from Figures 3.11 to 7.15 to this. Here the output is selected between port output or comparator output, and the input can be analog or digital. It is important to note that peripherals which share a pin with a port may be able to override the action of the TRIS register. For example in this figure the ‘Analog Input Mode’ line can disable digital input, while leaving the output path unaffected. The mechanism to do this is different from the 16F873A, and is outlined in Section 12.6.5.
An interesting example of optimising pin use is seen in pin 4 of Figure 12.1. Now an extra bit of Port A is added to the pin. Selection of pin function is made with the Master Clear Enable (MCLRE) bit in the Configuration Word. If RA5 is selected it is input only, and the clear function is then tied high internally.
Aside from changes in the port pin driver circuits, all other 16F88 peripherals are similar or identical to those of the 16F873A. Differences are identified in Table 12.1. Descriptions in Chapter 8, Chapter 9, Chapter 10 and Chapter 11 otherwise apply.
|16F88 peripheral||Difference from 16F873A implementation|
|Timer 1||Timer 1 oscillator can provide system clock, useful in providing a low-speed low-power mode.|
|CCP||There is only one module.|
|Synchronous Serial Port||Does not implement I2C Master mode, although this can be done in firmware.|
|ADC||Introduces the ANSEL register, to select whether input pins are analog or digital (see Section 12.6.5).|
12.3. The 16F883
As has been mentioned, the 16F883 is a possible upgrade for the 16F873A. The improvements it offers bring undoubted advantages, but they also bring complexity. This is illustrated immediately by the pin connection diagram of the ’F883, shown in Figure 12.4. A quick comparison with Figure 7.1 (a) shows that, like the 16F88, the pins are more loaded. Most of them now pick up three, four or even five alternative functions. It can be seen, however, that in all the complexity of the ’F883, each pin connection of the ’F873A can be found in the same place.
The block diagram of the 16F883 is shown in Figure 12.5. Not surprisingly, there are big similarities with the ’F873A diagram of Figure 7.2. The general structure, including all bus sizes, is the same. Ancillary features, like power supply and clock source, look similar, although the in-circuit debugger has migrated to a position connected to the data bus. We will find that the internal oscillator block is an important addition.
A reading of Ref. 12.2 shows that data and program memory maps for the 16F883 are very similar to the ’F873A, but reflect the small differences in memory sizes. The data memory map also includes the extra SFRs needed for the enhanced peripherals and other features. These are added into the memory map of Figure 7.6, making use of the previously unimplemented memory locations. The number of configuration bits of the ’F883 has gone up, now contained in two Configuration Words.
Compared with the 16F873A, the port bits have been extended cleverly in number and flexibility. If the internal oscillator is used (see Section 12.5) Port A can have a full eight bits, or seven if certain oscillator modes are used. In Port B, a weak pull-up can be individually enabled on each pin. This is in contrast to the old `all or nothing' approach, as controlled by bit 7 of the Option register (Figure 6.9). In a similar way, each Port B bit can be individually enabled to generate an interrupt on change. A single Port E bit is available if the function isn't used. Like the 16F88, the pin function is selected using the MCLRE configuration bit. If the port bit is selected it is input only, with then internally tied high.
Looking at the other peripherals, we find further differences. Usefully, the ’F883 diagram indicates which pin connections relate to each peripheral. We see that the CCP1 is replaced by an enhanced CCP (ECCP), and the USART is replaced by an enhanced USART (EUSART). These enhanced peripherals are outlined later in the chapter. Some of the SFRs associated with peripherals have been changed, for example those controlling the ADC. For this reason, the ’F883 is not necessarily exactly code-compatible with the ’F873A, if used as an upgrade for an existing design.
The diagram of Figure 7.10 shows that the 16F873A has 15 interrupt sources, all gated together to form a single interrupt to the CPU. The 16F883 interrupt structure takes this even further. Now there are eight possible Port B interrupt on change sources. There is also an ultra-low-power wake-up interrupt (outlined in Section 12.4), and a clock monitor interrupt. This brings the grand total of interrupt sources to a breath-taking 24, all still feeding into a single interrupt vector. This high number of interrupts increases by far the challenge of identifying the interrupt source by checking the flags, as we did back in Program Example 6.2.
12.4. NanoWatt technology
Many embedded systems are battery-powered and it is essential for them to consume as little power as possible. Techniques to reduce power are many and various. A fundamental point to recognise is that a logic circuit, particularly one made from CMOS (complementary metal-oxide semiconductor), consumes almost all its power on clock transitions. Therefore a system running from a low clock frequency consumes much less power than when it is running at high frequency. Explanation of this can be found in Ref. 1.1, or similar sources. The three main strategies for reduction of power consumption, for a given circuit and technology, are:
• Reducing the supply voltage.
• Minimising the clock frequency, possibly applying different frequencies at different times.
• Switching off unused circuit sections, or disconnecting them from the clock.
Manufacturers aim to minimise power consumption in their devices by providing features which facilitate the above points, for example the use of Sleep mode, introduced in Sections 6.6 and 9.11. They also aim to reduce internal power consumption by applying semiconductor technology which has very low internal leakage, and which has minimal consumption during any clock transition.
Microchip Technology introduced the nanoWatt Technology terminology in 2003, initially to identify and promote microcontrollers whose power consumption was measurable in nanoWatts (i.e. less than one microWatt) when in Sleep mode. This is illustrated in simple form in Table 12.2, drawn from Microchip data. The power consumption while in Sleep mode of both the 16LF88 and ’F883 is less than 1 μW, and hence qualifies for the nanoWatt technology tag. On the other hand the power consumption of the 16F873A under the same operating conditions is 2.7 μW; hence it does not qualify.
|Microcontroller||Sleep-mode current||Power consumption|
|16F873A||0.9 μA||2.7 μW|
|16LF88||0.3 μA||900 nW|
|16F883||0.15 μA||450 nW|
To the nanoWatt technology baseline definition are added a number of other possible features, like Idle mode, internal switchable oscillator, phase-locked loop, WDT with extended time-out, ultra-low-power wake-up, and others. These are used in varying combinations in microcontrollers which carry the nanoWatt technology label. The ones which appear in the 16F88 and 16F883 are shown in Table 12.3.
|NanoWatt technology feature||16F88||16F883|
|Internal oscillator block with switchable clock frequency||✓||✓|
|Two-speed clock start-up||✓||✓|
|Alternative clock source from Timer 1||✓||X|
|Extended WDT time-out||✓||✓|
As Table 12.3 shows, the 16F883 carries a number of nanoWatt technology features. For example, it has an extended range of WDT time-out periods, going up to 268 seconds. These can be used as for periodic wake-up when in Sleep mode. As long as the WDT is running, however, it consumes power. The 16F883 gives an alternative to this, the ultra-low-power wake-up (ULPWU), another of the nanoWatt technology special features. It uses the Port A bit 0 pin; the connection can be seen in Figure 12.4. Instead of a running clock, time is measured by the discharge of a capacitor, connected to this pin. While the microcontroller is awake, it charges the capacitor. When asleep, the capacitor very slowly discharges, with a current in the region of 100 to 200 nA, controlled by the pin driver circuitry. A comparator monitors the capacitor voltage and causes a wake-up when it has dropped to a certain value.
In 2009 Microchip introduced a new version of nanoWatt technology, called nanoWatt technology XLP (eXtra Low Power). This introduced a new mode called Deep Sleep, and took power consumption into new realms of efficiency. For more details on both versions of nanoWatt technology, see Ref. 12.3; further information on ultra-low-power wake-up can be found in Ref. 12.4.
12.5. Clock sources and their management
Microcontroller performance is intimately linked to its clock oscillator, as discussed in Section 3.5. Therefore, flexibility of the clock oscillator can be a key to successful design. The 16F88 and the 16F883 show similar innovations in clock oscillator design. Both contain an `internal oscillator block' within the microcontroller, giving a high degree of flexibility and the chance to run the microcontroller with no external clock connections. An internal oscillator in itself is not so extraordinary; RC clock sources have been integrated within microcontrollers for many years, for example the WDT clock in the 16F84A. To date such oscillators have been very low-precision, however – their frequency is not guaranteed with any accuracy and they are subject to temperature drift.
12.5.1. Clock sources
The block diagram of the 16F883 internal oscillator is shown in Figure 12.6. We see the conventional and familiar clock oscillator connections top left. Below these there are two internal oscillators: a high-frequency internal oscillator (HFINTOSC) and a low-frequency internal oscillator (LFINTOSC). The high-frequency oscillator is factory-calibrated, so a fair degree of accuracy is available. It is these internal oscillators, and their associated frequency division and selection circuits, which make the internal oscillator block, seen in Figure 12.5.
There is now some cleverness with how the clock source is chosen. It can be from the external oscillator, the internal high-frequency oscillator, from a divided-down version of the high-frequency oscillator, or the low-frequency oscillator. Choice of external oscillator type remains with the configuration bits, as seen in Figure 12.7 (a). Control of the internal oscillator block lies, however, with the OSCCON register, seen in Figure 12.7 (b).
The 16F883 has six possible external clock modes. These are all identified in both Figure 3.6 and Figure 3.7 (a). The four `traditional' modes, of LP, XT, HS and RC, are still there. These modes of operation are as described in Section 3.5.3. In the EC (external clock) mode of oscillator operation, an external clock source is connected to the OSC1 pin, a concept seen already in Figure 3.14 (c). As this mode needs only one pin as input, the OSC2 pin is taken to create an extra bit for Port A, bit RA6. A similar approach is taken with the RCIO mode – the RC clock oscillator only uses one pin, leaving pin OSC2 again available to be used as a port pin.
The configuration settings allow two further oscillator modes. The first of these, INTOSC, uses the internal oscillator and gives an output of Fosc/4 on the OSC2 pin. The second, INTOSCIO, uses the internal oscillator but does not make use of the OSC1 or OSC2 pins at all. These are thus both available for other purposes, and are used as bits 6 and 7 of Port A.
So how is clock source selected? Bit 0 of the OSCCON register, SCS, plays an important role. It can select between internal oscillator and the oscillator defined by the configuration bits. On reset this bit has a value of 0, so the clock source is initially defined by the configuration bits. These bits can of course be set to choose the internal oscillator, in which case SCS has little effect, and OSCCON can be set to choose the required clock speed. A more powerful combination is, however, to have an external oscillator, available for higher-speed, precision program sections, with the possibility to use SCS to switch over to an internal oscillator for lower-speed, lower-precision program sections. This offers a big step forward in controlling power consumption.
Due to its calibration, the high-frequency internal oscillator can be viewed as a possible complete replacement for an external crystal or RC combination. The data sheet states that HFINTOSC is accurate to within ± 1% of nominal value at 25oC and with a supply voltage of 3.5 V. It is accurate to within ± 2% between 0oC and 85oC, and ± 5% between 0oC and 125oC. These are useful values, though nowhere near the accuracy available from a good crystal oscillator. For these, ± 50 ppm (parts per million) initial tolerance at 25oC and ± 50 ppm frequency drift over an operating temperature range of −20oC to 70oC are readily available. The frequency of the internal oscillator can, however, be adjusted using the OSCTUNE register (not shown).
The low-frequency oscillator is not calibrated; the data states that its frequency may lie between 15 kHz and 45 kHz. Its use as a system clock source should therefore be reserved for low-speed, low-power applications or modes of operation, with no accuracy of timing required. As the diagram shows, it remains the clock source for watchdog and power-up timers, and the Fail-Safe Clock Monitor.
The 16F88 uses an internal oscillator block such as this one, but adds one further feature. The Timer 1 clock, if enabled, can be used as a further clock source option. This is particularly useful, as this can be a low-frequency crystal clock. Therefore, an accurate low-speed clock becomes available as an alternative to the main high-speed oscillator.
12.5.2. The Fail-Safe Clock Monitor
One of the less reliable parts of a microcontroller system can be its external clock oscillator. Soldered joints have a small inherent unreliability (hence everything external to the microcontroller chip can be considered to have a small reliability concern); moreover, a quartz crystal is a delicate item susceptible to mechanical shock. This is unfortunate, considering that without the clock oscillator the system will immediately fail. However, an internal RC oscillator has high reliability. With the choice of clock sources now available, and the reliability concerns just mentioned, it is worth monitoring any external clock oscillator, and arranging a source switch if the primary one fails.
The Fail-Safe Clock Monitor (FSCM) does just this, repeatedly checking that the external oscillator is running. It monitors any of the external oscillator modes. If the oscillator is found to have failed, the FSCM forces a switch to the internal clock source defined by the IRCF bits in the OSCON register. This allows operation to continue, though probably at a slower rate and with less precision. (A similar mode is poetically called `limp-home' in some Freescale microcontrollers.) Clock failure also causes an interrupt. A response to this failure condition can therefore be programmed into the system firmware. The FSCM is enabled by setting the FCMEN configuration bit.
12.6. Some enhanced peripherals
While many peripherals in the 16F883 are unchanged from their equivalents in the ’F873A, others experience either minor changes or major enhancements. These are reviewed below.
12.6.1. The timers
The 16F883 Timers 0 and 2 are broadly the same as the ’F873A. A small but important change to Timer 1 is that it can be gated (i.e. enabled or disabled). This can be through the input (pin 26, Figure 12.4), which can be used to time digital events like pulse widths. Alternatively it can be gated through the output of Comparator 2. In this case the duration of analog voltage excursions can be timed, for example for how long a particular input moves above a reference voltage.
12.6.2. The enhanced capture, compare and pulse width modulation module
There are two CCP modules in the 16F883. This can be seen in Figure 12.5. Module CCP2 is standard, but CCP1 is enhanced and is labelled `ECCP' in the figure. In either module, capture and compare are unchanged, so Figures 9.8 and Figures 9.9 continue to apply. The enhancement lies only with how the PWM pulse streams can be manipulated and output.
The enhanced CCP is shown in block diagram form in Figure 12.8. The PWM source now has an output controller, and four PWM outputs. These are labelled PIA to PID, and can be seen in Figure 12.4. The actual generation of the PWM stream in the enhanced CCP is unchanged, so Figure 9.11, Figure 9.12, Equation (9.2) and Equation (9.3) continue to apply. The enhancement allows a range of features that are required when applying PWM in advanced motor control applications. This includes direct driving of half and full bridges, the introduction of `dead time' between pulses, the ability to easily to reverse motor direction, and auto-shutdown. A full H-bridge can for example be connected as in Figure 12.9, with the ability to exert considerable control over each individual signal. The price of course is that four microcontroller pins are now committed to just one H-bridge circuit. The ability to control PWM signals here is for advanced applications, and goes well beyond the simple approach used for the Derbot motor drive.
12.6.4. The enhanced addressable USART
In basic operation this module acts like the standard USART, described in Section 10.10. It also has some interesting developments. One of these is automatic baud rate detection, useful in the Local Interconnect Network protocol (LIN, see Chapter 20) and other applications. The process is illustrated in the timing diagram of Figure 12.10. To undertake detection, the ABDEN bit (of the Baud control register, BAUDCTL) is set by the user. At this point, the frequency of the Baud Rate Generator (BRG) clock is reduced to one-eighth of its current setting. To operate correctly, the byte 55H, or 1010 1010B, must be received. This incidentally is the SYNC character of the LIN protocol. The duration from first rising edge on the RX pin to the last is then timed. This is done using the slowed BRG clock. A 16-bit counter configured within the baud rate generator (made of registers SPBRGH:SPBRG) is used to count BRG clock cycles. On the final rising edge, the ABDEN bit is automatically cleared. Because the counter measures the duration of eight incoming serial bits, and it is running temporarily at one-eighth of its current setting, a measurement has effectively been made of one bit duration. This can then be used to set the baud rate for further reception of serial data.
Another enhancement in the EUSART is its automatic wake-up. It would be useful if the EUSART could cause a wake from Sleep, but with all clocks to it suspended in Sleep this seems impossible. Once automatic wake-up is enabled, however (through bit WUE of the BAUDCTL register), the EUSART waits for a high to low transition on the Receive line, i.e. the transition from idle to start. This happens whether or not the CPU is in Sleep mode. When the transition occurs it generates an interrupt, which can be used to wake from Sleep. The EUSART module returns to normal operation when the next low to high transition occurs. Therefore the characters used for wake-up should be all zeros, otherwise the rising edge will be detected within the word and the remainder of the word will be detected incorrectly as a new character. Once again, this facility is useful in LIN applications, and is another mechanism for adapting the microcontroller to the extreme low-power environment.
12.6.5. The analog-to-digital converter module
The ADC of the 16F883 is shown in Figure 12.11. While it is drawn differently, it is in fact similar to Figure 11.6: the ADC of the 16F873A. A big difference however, is the larger number of inputs. These occupy Port A, as with the ’F873A, but also now spread across Port B (as Figure 12.4 shows). Aside from regular analog inputs, it is also possible to select an internal 0.6 V fixed voltage reference as input, or the comparator reference, CVREF. The voltage reference is shown connected to the top of the ADC block. This can be derived from the power supply, or from external connections coming in through inputs 2 and 3.
ADC operation is controlled by registers ADCON0 and ADCON1, but these are not the same as in Figure 11.7 and Figure 11.8. Notably, configuration of the input is now controlled by a new pair of registers, ANSEL and ANSELH, as has already been mentioned in connection with port bit control. This marks a change from the 16F873A, where it is register ADCON1 which configures the input pins. The ANSEL register is shown in Figure 12.12. It is easy to see that each register bit controls one analog input bit. When the bit is low the pin is available for digital input, and analog when it is high. One bit is seen in action in Figure 12.3, where it is labelled ‘Analog Input Mode’.
A weakness of the 16F873A ADC module is its relatively long acquisition time, as discussed in Section 11.3.4. This is determined by the resistance of source and input path and the hold capacitance, seen in the input model of Figure 11.10. If multiple inputs are being scanned, as is now possible, this lengthy acquisition time is a real disadvantage. It is interesting to note therefore that although the ADC under discussion keeps the input model of Figure 11.10, the hold capacitance is reduced dramatically, from 120 pF to 10 pF. The acquisition time formulae derived in Section 11.2.4 continues to apply, but acquisition time is now effectively one-twelfth of the values calculated in that chapter.
This short chapter has aimed to introduce some enhancements to the PIC microcontroller range, and in so doing to illustrate some more advanced techniques in embedded systems. All enhancements are applicable to the 16 Series microcontrollers, but many also find their place in other families, for example in the 18 Series. The main points are:
• The 16F87/88 microcontrollers represent a possible upgrade path for the 16F84A.
• The 16F88X group represents a possible upgrade path for the 16F87XA; in this and the above case, the upgrade group brings greater sophistication, but also greater complexity.
• NanoWatt technology is a grouping of technologies and techniques which allows absolute minimisation of power consumption.
12.1. PIC 16F87/88 Data Sheet (2005). Microchip Technology Inc., Document no. DS30487C; www.microchip.com
12.2. PIC16F882/883/884/886/887 Data Sheet (2008). Microchip Technology Inc., Document no. DS41291E; www.microchip.com
12.3. nanoWatt and nanoWatt XLP Technologies: an Introduction to Microchip's Low-Power Devices (2009). Microchip Technology Inc., Application Note AN1267, Document no. DS01267A.
12.4. Using the Microchip Ultra Low-Power Wake-Up Module (2008). Microchip Technology Inc., Application Note AN879, Document no. AN00879D.
Note: Access toReference 12.1will be required for most or all of these questions.
1. In a 16F883 the TICON register is set to 1101 1111, and CM2CON1 is set to 0000 0010. Inputs to Timer 1 are connected to a 32.768 kHz crystal. Timer 1 is cleared to zero and a short while later a positive-going pulse occurs on pin 26, which was previously at Logic 0. When the pulse has returned to zero, Timer 1 is read and found to hold the value 01011100 10100011. If Timer 1 did not overflow during the pulse, what was its duration?
2. An 8.000 MHz crystal is connected to pins 9 and 10 of a 16F883, and the FOSC<2:0> bits in the configuration register are set to 010. At one moment in the program's operation the OSCCON register reads 0011 1110, and a little later it reads 0011 0111. What is the system clock frequency in each case?
3. The WDT of a 16F883 is configured to overflow approximately every 67 seconds, to wake the microcontroller from sleep. It is then awake for 12 ms, during which time it consumes 2.4 mA. The 16F883 is powered from 3 V and consumes 5.5 μA when in Sleep mode, with WDT running.
(a) What is the average current consumption?
(b) The WDT is replaced with an ultra-low-power wake-up. For this the capacitor discharge current is 135 nA. The current consumption of the microcontroller itself while in Sleep is otherwise 1.5 μA. All other conditions are adjusted to be the same. What is the new average current consumption? (Note that the current needed to charge the ULPWU capacitor is neglected in this example.)
4. A 16F883 microcontroller is operating from a supply of 4 V. The ADC is used, but only 8-bit accuracy is required. The signal source resistance is 5 kΩ. Estimate the acquisition time required. (Note the similarity of this question to Question 4 of Chapter 11.)
5. The BRG clock of a 16F883 EUSART is free running at 614.4 kHz when the ABDEN bit is set high. The digit 55H is subsequently received. When the RCIF flag goes high, the SPBRGH:SPBRG counter is found to hold 0040 H. What was the measured bit rate?
6. A 16F883 is powered from 4.8V. Its ADC is set as follows:
CHS<3:0> = 1111; VCFG1 = 0; VCFG0 = 0; ADFM = 1; ADON = 1.