## Chapter 2

## Basic Circuit Laws

##### CHAPTER OBJECTIVES

*To state and explain Kirchhoff’s Current Law and Kirchhoff’s Voltage Law*.*To explain the different ways of stating these laws*.*To illustrate the application of these laws in Circuit Analysis by examples*.*To introduce Operational Amplifier and to illustrate application of Kirchhoff’s laws in analysis of Operational Amplifier circuits*

##### INTRODUCTION

The electrical devices in an electrical system under quasi-static conditions are modelled by ideal two-terminal elements or multi-terminal elements. The ‘circuit model’ of the system is obtained by interconnecting the elements by means of connecting wires that are assumed to be of infinite conductivity and near-zero cross-sectional area. Interconnecting electrical elements into a ‘circuit’ will result in ‘junctions’ at which the connecting wire-ends of two or more two-terminal elements or multi-terminal elements will join together. Such junctions are called *nodes *in Circuit Analysis. Further, interconnection of elements will result in one or more closed paths involving two or more elements. Such closed paths comprising elements and nodes are called *loops *in Circuit Analysis.

Each two-terminal element is completely described by two variables – one terminal voltage variable *v*(*t*) and one element current variable *i*(*t*)*. *Passive sign convention is assumed in assigning reference directions for these variables. The *element relations *of two-terminal elements are known. The relation is in the form of an equation relating *v*(*t*) and *i*(*t*) in the case of passive elements. It is in the form of constraints on *v*(*t*) or *i*(*t*) in the case of ideal independent sources.

Each four-terminal element will be described by two voltage variables and two current variables – one voltage variable and one current variable per terminal pair. Two relations tying up these variables or constraining them will be available for each such four-terminal element. For instance, consider a voltage-controlled voltage source. There is an open-circuit across its first terminal pair and there is a voltage source across its second terminal pair.

We treat each four-terminal element as two two-terminal elements with some relation between their voltage and current variables, as far as element count in a circuit is concerned. Let there be *b-*elements, *n-*nodes and *l-*loops in a lumped parameter circuit. Then there are 2*b* variables – *b *terminal voltage variables and *b *element current variables – to be solved for in the circuit. We call these variables the *element variables. *

Each element contributes either an equation relating its voltage variable to its current variable or a constraint equation which imposes a constraint on either its current variable or voltage variable. Thus, we get *b *equations in 2*b* variables from *element relations *alone. These equations are independent of the manner in which the circuit elements are interconnected. They depend only on the nature and parameter value of the individual elements. We call this set of *b *equations involving 2*b* element variables the *element equation set. *

We need another set of *b *independent equations on 2*b* element variables to solve for all the element variables. These equations will have to be independent of the *element equation set. *They come from the interconnection details of the circuit. *They depend only on how the elements are interconnected and will not depend on the nature or parameter value of elements. *That is, they depend only on the *topology *of the circuit. This set of *b *independent equations that summarises the constraints imposed on 2*b* element variables by the interconnection is called the *interconnection equation set. *‘Element equation set’ and ‘Interconnection equation set’ provide the complete set of equations needed to solve for all the element variables in a circuit.

The interconnection equation set is obtained by applying two basic conservation laws of physics to the circuit. The laws of conservation of energy and charge have been restated in a form suitable for applying to lumped parameter circuits. Gustav Robert Kirchhoff arrived at the required restatements of these conservation laws in 1857 and they are called *Kirchhoff’s Voltage Law *(*KVL*) and *Kirchhoff’s Current Law *(*KCL*)*. *

Kirchhoff ’s Voltage Law imposes a constraint on the voltage variables appearing in a loop in the circuit. Applying this law to a loop in the circuit results in a single constraint equation involving an algebraic sum of all the voltage variables that appear in the loop. Kirchhoff ’s Current Law imposes a constraint on the current variables appearing at a node in the circuit. Applying this law to a node in the circuit results in a single constraint equation involving an algebraic sum of all the current variables that appear at the node. These constraint equations are algebraic in form.

##### 2.1 KIRCHHOFF’S VOLTAGE LAW (KVL)

Consider a DC circuit with many loops as shown in Fig. 2.1-1. Six two-terminal elements are interconnected in this 4-node circuit. The interconnection results in 7 loops in the circuit. The loops are 1–4–2, 2–5–3, 4–6–5, 1–6–3, 1–4–5–3, 2–4–6–3 and 1–6–5–2. The elements are numbered and encircled numbers label the nodes.

**Fig. 2.1-1** A DC Circuit with 6-elements, 4-nodes and 7-loops

The circuit is assumed to be in DC steady-state. That is, all the sources in the circuit are assumed to be constants and all the circuit variables are assumed to be constants in time.

Thus, the charge distribution at the terminals and on the surface of each two-terminal element in the circuit is steady in time. The charge distribution produces electrostatic field everywhere. The electrostatic field generated within an element and in the immediate vicinity of an element is proportional to the charge stored on that element. (This is a standard assumption in lumped parameter circuit theory as pointed out in Chap. 1.) The voltage variables marked in Fig. 2.1-1 are the electrostatic potential differences that exist between the terminals of elements. The connecting wires have zero resistance. Moreover, there is no charge distribution on the surface of connecting wires.

Imagine that we are carrying a unit positive test charge from node-4 back to the same node by moving it along the path shown by dotted curve in Fig. 2.1-1 in the counter-clockwise direction. The path of travel touches node-1 and node-3. Electrostatic field is a conservative field. Only electrostatic field is present at points lying on the path of travel of unit positive test charge. Therefore, the work to be done in moving the unit positive test charge around this closed path must be zero. *v*_{1} J is the work to be done in moving a unit positive test charge from node-4 to node-1. *v*_{2} J is the work to be done in moving a unit positive test charge from node-3 to node-1. And, *v*_{3} J is the work to be done in moving a unit positive test charge from node-4 to node-3. Therefore, the work to be done in moving a unit positive test charge from node-4 to node-4 by moving in the dotted path in counter-clockwise direction = (The work to be done in moving a unit positive test charge from node-4 to node-1) + (The work to be done in moving a unit positive test charge from node-1 to node-3) + (The work to be done in moving a unit positive test charge from node-3 to node-4) = *v*_{1} – *v*_{6} – *v*_{3}. This has to be zero. Therefore, conservative nature of electrostatic field leads to the following equation involving the three voltage variables appearing in the loop formed by element-1, element-6 and element-3:

*v*

_{1}–

*v*

_{6}–

*v*

_{3}= 0 (2.1-1)

If we had taken a unit positive test charge around the same path in clockwise direction, we would have obtained the following equation:

*v*

_{3}+

*v*

_{6}–

*v*

_{1}= 0 (2.1-2)

Obviously, Eqn. 2.1-2 must be Eqn. 2.1-1 multiplied by –1. Thus, the direction of traverse of the loop does not matter when we prepare the equation involving voltage variables appearing in that loop.

Now we dispense with the dotted path altogether. Instead, we traverse the loop formed by element-1, element-6 and element-3 in the counter-clockwise direction, starting from node-4. We collect the * voltage rise amounts across each element* as we go along and enter these quantities into a sum. Obviously, in this process we are calculating the total work to be done in carrying a unit positive test charge through a path outside the elements, but touching the nodes. Therefore this sum must be zero. The * voltage rise* across the element-1 in the direction of traverse (counter-clockwise direction) is *v*_{1}. The * voltage rise* across the element-6 in the direction of traverse is –*v*_{6}. The * voltage rise* across the element-3 in the direction of traverse is –*v*_{3}. Therefore, the sum of voltage rises encountered in traversing the loop formed by element-1, element-6 and element-3 in the counter-clockwise direction is *v*_{1} – *v*_{6} – *v*_{3}. We have already verified that this sum must be equal to zero due to conservative nature of electrostatic field.

If we collect the * voltage drop amounts across each element* as we traverse the loop in counter-clockwise direction and enter them in a sum, we get – *v*_{1} + *v*_{6} + *v*_{3}. This sum is equal to zero since this is the work to be done in taking a unit positive test charge around the dotted path in clockwise direction.

Similarly, we could have traversed the loop in clockwise direction and collected the * voltage rises. * The sum of * voltage rises* encountered will be *v*_{3} + *v*_{6} – *v*_{1} and will be equal to zero. If * voltage drops* are collected instead, the sum of * voltage drops* will be –*v*_{3} – *v*_{6} + *v*_{1} and will be equal to zero.

Or, we could have entered the element voltages that we encounter when we traverse the loop in *counter-clockwise* direction in a sum, with the sign for a particular element voltage variable same as the * polarity of the variable that we meet first when we reach that element.* – *v*_{1} + *v*_{6 } + *v*_{3} is the result and it is equal to zero. The sum that is formed in this case is called the * algebraic sum of voltages.*

Or we could have formed the * algebraic sum of voltages* encountered when we traverse the loop in *clockwise* direction. *v*_{3} + *v*_{6} – *v*_{1} is the result and it is equal to zero.

Hence, the constraint appearing among voltage variables of elements in a loop can be obtained by any of the following methods:

- Traversing the loop in
*clockwise*direction and equating the sum of*voltage rises*encountered to zero. - Traversing the loop in
*clockwise*direction and equating the sum of*voltage drops*encountered to zero. - Traversing the loop in
*counter-clockwise*direction and equating the sum of*voltage rises*encountered to zero. - Traversing the loop in
*counter-clockwise*direction and equating the sum of*voltage drops*encountered to zero. - Traversing the loop in
*counter-clockwise*direction and equating the*algebraic sum of voltages*encountered to zero. - Traversing the loop in
*clockwise*direction and equating the*algebraic sum of voltages*encountered to zero.

All the six methods will lead to the same constraint equation. However, in the interest of systematic formulation of circuit equations, it is imperative that we adhere to any one method consistently. We choose the last method in this book. * Hence, in this book, voltage constraint equations are written by traversing the loop in clockwise direction and equating the algebraic sum of voltages encountered to zero.*

There was nothing special about the particular loop that was chosen to demonstrate the implications arising out of conservative nature of electrostatic field as far as voltage variables in a circuit are concerned. Hence, the same line of reasoning is applicable to all loops in the circuit. Therefore, at least for a DC circuit under steady-state, we can generalise the aforementioned conclusions into the following law:

**Fig. 2.1-2 **A 4-node, 6-element, 7-loop circuit with time-varying voltages and currents

‘*The algebraic sum of voltages in any closed path in a circuit is zero*.’ * This is called Kirchhoff’s Voltage Law.*

Will this law hold good for circuits with time-varying voltage variables too? Consider the same circuit with time-varying voltage variables now as in Fig. 2.1-2.

Lumped parameter circuit theory assumes that the induced electric field component caused by time-varying currents in the circuit is negligible everywhere in the space surrounding the devices. Thus, the only force field that is present in the space outside circuit elements is the field generated by the coulomb force (i.e., the force that depends only on charges and the distance between charges as per inverse square law) arising out of charge distributions on the circuit elements. The quantity of charge stored in each element in a circuit will change with time in a circuit containing time-varying sources. Therefore, the force field in the space outside the elements also will vary with time. However, at any instant * t,* the force field is dependent only on the charges stored in elements at that instant and the spatial distances involved. The term ‘electrostatic field’ does not imply that the value and direction of this field are constant in time. Rather, it means that the field arises out of ‘coulomb force term’. Thus, we can use the term ‘electrostatic field’ to represent the force field arising out of ‘coulomb force terms’ even when the charge distributions on the elements vary with time.

*The conservative nature of a force field arising out of ‘coulomb force’ is a direct result of inverse square dependence on distances displayed by such forces.* Therefore, if only coulomb force field is present in the space surrounding a circuit, the work integral – [ * i.e., * where is the ‘coulomb force field’ or electrostatic field], evaluated at any instant * t* over any closed path lying outside the circuit elements, will be zero quite irrespective of whether the ‘coulomb force field’ is time-varying or not. Therefore, the algebraic sum of instantaneous value of voltage variables in any loop in the circuit must be zero.

However, we have been accustomed to interpret the work integral as the work to be done in carrying a unit positive test charge around a closed path in the field quasi-statically. We face a problem in carrying over this interpretation to a time-varying situation. We have to move this unit test charge slowly around the loop. But then, the work we calculate will be the work done against at different instants at different locations since we cannot be moving that test charge with infinite speed in the closed path. That is not the same as the value of integral at a particular time instant *t*.

However, the only field that is present in the space around elements in a time-varying circuit is the electrostatic field. Therefore, the field outside the elements at any instant * t* will be the same as the *electrostatic field* that would exist in a * DC circuit* with same elements and same geometry, but with all charge variables, voltage variables and current variables in the circuit frozen at the values they had at the time instant *t*. Imagine that we are carrying a unit positive test charge around a closed loop in this * frozen circuit.* The work to be done in this process will be zero since the charge was taken around a closed path in a * steady conservative field.* Therefore, the algebraic sum of voltage variables in any loop in this * frozen circuit* must be zero. But, this will imply that the algebraic sum of instantaneous value of voltage variables, at any *t*, in any loop in the circuit with time-varying voltages, must be equal to zero.

Therefore, KVL is valid also under time-varying conditions. The complete statement of KVL follows:

Kirchhoff’s Voltage Law states that the algebraic sum of voltages in any closed path in a lumped parameter circuit is zero on an instant-to-instant basis.

It may alternatively be stated in terms of * voltage rises* or * voltage drops* as follow:

Kirchhoff’s Voltage Law states that the sum of ‘voltage rises’ in any closed path in a lumped parameter circuit is zero on an instant-to-instant to basis.

Kirchhoff’s Voltage Law states that the sum of ‘voltage drops’ in any closed path in a lumped parameter circuit is zero on an instant-to-instant to basis.

The circuit in Fig. 2.1-2 has 7 loops. The loops are 1–4–2, 2–5–3, 4–6–5, 1–6–3, 1–4–5–3, 2–4–6–3 and 1–6–5–2, where the numbers refer to the element labels.

The KVL equations for these loops are derived in the following

We observe that the first three equations will form an independent set of three equations. But the fifth equation can be obtained by adding the first two equations together. When Loop 1–4–2 equation is added to Loop 2–5–3 equation, the term *v*_{2}(*t*) appears twice with opposite signs. Thus the resulting equation must be that of a loop formed by 1–4–5–3. Similarly, Loop 2–5–3 equation added to Loop 4–6–5 equation should result in Loop 2–4–6–3 equation. Sum of the first three equations must be same as the fourth equation.

Thus, not all the seven equations are independent. In fact, in a non-degenerate circuit containing *b*-elements, *n*-nodes and *l*-loops there will be exactly (*b* – * n +* 1) loop equations that are independent. *l* will be more than or equal to (*b* – * n +* 1). These statements come from a branch of study called Network Topology. We accept these statements without proof at this point.

This does not mean that a random selection of (*b* – * n* + 1) loop equations from the set of * l* loop equations will be an independent set of loop equations. For instance, in the present example, there must be (6 – 4 + 1) = 3 independent loop equations. However, the loop equations for Loop 1–4–2, Loop 2–5–3 and Loop 1–4–5–3 are not independent. The third can be obtained by adding the first two. Note that the first two loops are completely contained by the third loop. A *planar circuit* is one that can be drawn on paper without any crossing of connection wires. A * basic window* in a * planar circuit* is a loop that does not contain any other loop within it. It must be intuitively clear that the loop equations for the * basic windows* of the * planar circuit* will form an independent set of loop equations. These * basic windows* of a * planar circuit* are called its ‘*meshes*’.

** Example: 2.1-1**

The source voltages of four independent voltage sources in the circuit in Fig. 2.1-3 are given as *v _{S}*

_{1}= 10 V,

*v*

_{S}_{2}= 10sin100

*t*V,

*v*

_{S}_{3}= 10cos100

*t*V and

*v*

_{S}_{4}= 10 V.

*v*

_{3}is observed to have a zero average value. The time-varying component of

*v*

_{1}is seen to be 10sin(100

*t*–30°) V. Find

*v*

_{1},

*v*

_{2}and

*v*

_{3}as functions of time.

**Fig. 2.1-3** Circuit for Example: 2.1-1

**Solution**

*v*_{3} is stated to have a zero average. This implies that *v*_{3} has a zero DC content. Thus, *v*_{3} can be written as *v*_{3} = * A* sin(100*t* –* θ*) V where * A* and * θ* are to be found. *v*_{1} is stated to have a time-varying component of 10sin(100*t*–30°) V. It may have a DC content too. Thus, *v*_{1} = * B +* 10 sin(100*t*–30°) V, where * B* is to be found. *v*_{2} may contain both DC and time-varying components. Thus, *v*_{2} = * C + D *sin(100*t* – *ϕ*) V, where *C*, * D* and *ϕ* have to be found.

Apply KVL in the first loop. The KVL equation is:

–*v _{S}*

_{1}+

*v*

_{1}+

*v*

_{3}+

*v*

_{S}_{2}= 0

*i.e*., –10+(*B*+10sin(100*t* – 30º))+ *A*sin(100*t*–*θ*)+10sin100*t* = 0

This equation involves some constants and some sinusoidal functions. This equation is the result of applying KVL to a loop in a circuit. Therefore, this equation has to be true at all * t.* Therefore, the equation can be split into two equations that have to be satisfied simultaneously. This is because a constant can not be met by a sinusoidal function in an equation for all * t.*

*B*= 0 and 10 sin(100

*t*– 30º) +

*A*sin(100

*t*–

*θ*) +10 sin100

*t*= 0

First equation yields * B* = 10 V. Second equation is simplified by employing trigonometric identities as below:

This equation can be true for all * t* only if the coefficient of sin100*t* is zero and the coefficient of cos100*t* is zero independently.

Now apply KVL in the outer loop to get,

Therefore, *v*_{1} = 10 + 10sin(100*t* – 30°) V*, v*_{2}* =* 10 + 19.32sin(100*t* + 15°)V and v3 = 19.32 sin(100*t* – 195°) V is the required answer.

The key to the solution of this problem is the point that KVL has to be satisfied at all time instants.

**Example: 2.1-2**

Express the terminal voltages of elements 2, 3 and 5 in terms of terminal voltages of elements 1, 4 and 6 in the circuit in Fig. 2.1-4.

**Fig. 2.1-4** Circuit for Example 2.1-2

**Solution**

Applying KVL in the loop 1–4–2, we get, –*v*_{1}(*t*)+*v*_{4}(*t*)+*v*_{2}(*t*) = 0.

∴ *v*_{2}(*t*) =* v*_{1}(*t*) – *v*_{4}(*t*)

Applying KVL in the loop 4–5–6, we get, *v*_{4}(*t*)+*v*_{5}(*t*)–*v*_{6}(*t*) = 0.

∴ *v*_{5}(*t*) =* v*_{6}(*t*) – *v*_{4}(*t*)

Applying KVL in the loop 1–6–3, we get, –*v*_{1}(*t*)+*v*_{6}(*t*)+*v*_{3}(*t*) = 0

∴ *v*_{3}(*t*) =* v*_{1}(*t*) – *v*_{6}(*t*)

##### 2.2 KIRCHHOFF’S CURRENT LAW

Conservation law of charge states that charges can neither be created nor destroyed in a given volume. Hence, if the positive charge that flows into a volume at any instant * t* exceeds the positive charge that flows out of the volume at the same instant, then the net charge stored inside the volume must be increasing at that instant. Similarly, if the positive charge that flows out of the volume exceeds the positive charge that flows into the volume at that instant, then the net charge stored within must be decreasing at that instant. Therefore, the * net positive current* that flows into the volume at an instant * t* must be equal to the * rate of change* of * net charge* stored within that volume at that instant. A mathematical statement of this fact is called the * continuity equation for currents.*

If, for some reason, the net charge inside the volume is either constrained to remain at zero at all instants or is constrained to remain at some constant value at all instants, then the * net positive current * that flows into the volume must be zero at all instants.

Lumped parameter circuit theory assumes that the surface charge distribution on the surface of connecting wires is negligible at all instants of time. There is surface charge distribution on all circuit elements other than the connecting wires. In general, these surface charge distributions are time-varying too. However, the positive and negative charges distributed on the surface of any two-terminal or four-terminal element are equal in magnitude at all time instants under quasi-static conditions. Therefore, if we consider a volume that contains some circuit elements completely within, those elements will contribute only zero net charge to the net charge storage within the volume. The situation would, however, be different if the volume intersects some element. For instance, consider a volume that encloses only one of the plates of a capacitor. Then, there will be net charge storage within the volume and that may change with time too.

Therefore, we restrict ourselves to a volume that intersects connecting wires at many places without enclosing or intersecting even a single circuit element or a volume that intersects connecting wires at many places and completely encloses one or more circuit elements. We do not permit the volume to intersect any circuit element.

Since an element completely enclosed within a volume does not contribute to net charge within the volume and since the connecting wires have only negligible surface charge distributions on them, it follows that the net charge contained in a volume chosen the way suggested in the previous paragraph will be zero at all * t.* Therefore, the rate of change of net charge will also be zero at all *t*. * Then, by continuity equation for currents, the net positive current that flows into the volume through the wires must be zero at all time-instants.*

A * node* in a circuit is a part of the connecting wire. Therefore, there is no charge storage at a * node * in a circuit as per the assumptions employed by lumped parameter circuit theory. Therefore, there is no rate of change of charge storage too. Consider a special volume – a volume that encloses a node in a circuit and intersects all the wires connected at that node. Then, the reasoning outlined above leads us to the conclusion that the *net positive current* that flows into the volume through all the connecting wires that were intersected by the volume (*i.e.,* all the wires connected together at that node) should be zero at all *t*. Equivalently, we may state that, * net positive current* that flows out of the volume must be zero at all *t*.

**Fig. 2.2-1** Circuit for illustrating kirchhoff’s current law

Consider a volume denoted by the dotted circle around node-2 in the circuit in Fig. 2.2-1. This volume intersects three wires and encloses the node-2. It does not enclose any circuit element nor does it intersect any circuit element other than the connecting wires. Therefore, the * net positive* *current flowing out of the volume* must be zero. This fact leads to the following equation:

*i*

_{4}(

*t*)+

*i*

_{2}(

*t*)+

*i*

_{5}(

*t*) = 0 (2.2-1)

where* i*_{4}(*t*) is a current that flows * into* the volume. We need a minus sign to make it a current that flows *out of* the volume. Hence the minus sign in front of *i*_{4}(*t*) in Eqn. 2.2-1.

We could have arrived at an equation containing the same information contained in Eqn. 2.2-1 by stipulating that the * net positive current flowing into the volume* must be equal to zero. The resulting equation will be:

*i*

_{4}(

*t*)–

*i*

_{2}(

*t*)–

*i*

_{5}(

*t*) = 0 (2.2-2)

Eqn. 2.2-2 is, obviously, Eqn. 2.2-1 multiplied by –1 and contains the same information.

We could have arrived at Eqn. 2.2-1 by stipulating that the * algebraic sum* of currents * leaving* a node must be equal to zero. ‘ *Algebraic sum*’ in this case implies that if a particular current variable has its * reference direction* pointing * towards* the node, it has to enter the equation with * negative* sign. If a particular current variable has its * reference direction* pointing * away* from node, it has to be entered in the equation with * positive* sign.

Similarly, we could have arrived at Eqn. 2.2-2 by stipulating that the * algebraic sum* of currents *entering* a node must be equal to zero. ‘*Algebraic sum*’ in this case implies that if a particular current variable has its * reference direction* pointing * towards* the node, it has to enter the equation with a *positive* sign. If a particular current variable has its * reference direction* pointing * away* from node, it has to be entered in the equation with * negative* sign.

Obviously, all the four methods of arriving at the node equation are equivalent. However, in the interest of a systematic procedure, we use the stipulation that the * algebraic sum* of currents * leaving* a node must be equal to zero. We are ready to state the Kirchhoff’s current law now.

Kirchhoff’s Current Law (KVL) states that the algebraic sum of currents leaving a node in a lumped parameter circuit is equal to zero on an instant-to-instant basis.

KCL at a node can be stated in alternative ways.

Kirchhoff’s Current Law (KVL) states that the algebraic sum of currents entering a node in a lumped parameter circuit is equal to zero on an instant-to-instant basis.

Kirchhoff’s Current Law (KVL) states that the sum of currents entering a node in a lumped parameter circuit through some wires must be equal to the sum of currents leaving the same node through the remaining wires on an instant-to-instant basis.

KCL equations at all nodes of the circuit shown in Fig. 2.2-1 are derived in the following:

Note that the sum of these equations will be of 0 = 0 form. This indicates that these five equations do not form an independent set of equations. If we add all KCL equations derived for all the nodes of a circuit, a particular current variable that enters some equation with a positive sign will necessarily enter some other equation in the set with a negative sign. After all, an element has to get connected to two nodes. Therefore, all terms on the left-hand side of the sum will get cancelled. Suppose we discard the KCL equation at any one node. At least two elements must be connected to any node. Therefore, the sum of four of the five KCL equations will have at least two current variables present on the left-hand side. Therefore, any set of four KCL equations will be an independent set of equations. * Thus, in general, there will be* *(n–1) independent KCL equations in an n-node circuit.*

We had earlier accepted the fact that there will be (*b* – * n +* 1) independent KVL equations for a *b*-element, *n*-node,* l*-loop lumped parameter circuit. (*b* – * n +* 1) independent KVL equations together with (*n*–1) independent KCL equations make the required * b* interconnection equations needed to solve the circuit.

It is possible to arrive at a more general form of KCL applicable to lumped parameter circuits by considering a closed surface that encloses more than one node along with one or more elements. We have reasoned earlier in this section that the net charge contained inside such a closed surface must be equal to zero. Therefore, the algebraic sum of currents leaving such a closed surface must be equal to zero on an instant-to-instant basis. Such a closed surface will contain two or more nodes, and all the elements that are connected between the nodes are within the closed surface. Such a closed surface is called a * supernode.*

How many nodes can a circuit with * n* nodes have? Taking two at a time, there are ^{n}*C*_{2 } supernodes that contain two nodes each. Similarly, there are ^{n}*C*_{3} supernodes that contain three nodes each. See the circuit in Fig. 2.2-2.

**Fig. 2.2-2 **(a) Circuit showing two supernodes with two nodes each

(b) Circuit showing a supernode that contains three nodes

Two supernodes, each containing two nodes, are shown in the circuit in Fig. 2.2-2(a). One supernode containing three nodes is shown in the circuit in Fig. 2.2-2(b).

#### Kirchhoff’s Current Law is applicable to supernodes too

Therefore, the KCL equation for the supernode containing node-1 and node-2 is obtained as *–i*_{1}(*t*) + * i*_{6}(*t*) + * i*_{2}(*t*) + * i*_{5}(*t*) = 0. Obviously, this must be the sum of KCL equations written for node-1 and node-2. Similarly, the KCL equation for the supernode in the circuit in Fig. 2.2-2(b) must be the sum of KCL equations written for node-1, node-2 and node-5. This may be verified.

The total number of KCL equations that can be written for an *n*-node circuit is equal to ^{n}*C*_{1}+^{n}*C*_{2 }+^{n}*C*_{3}+…+^{n}*C*_{n–1}. This series has a sum equal to 2^{n} – 2.

Only (*n* – 1) independent equations from these 2^{n} – 2 KCL equations can be used for solving the circuit.

**Example: 2.2-1**

Find the power delivered by all the sources in the circuit in Fig. 2.2-3.

**Solution**

Currents through the voltage sources and voltage across the current sources have to be obtained first. The circuit with all nodes and reference directions for variables identified is shown in Fig. 2.2-4.

**Fig. 2.2-3** Circuit for Example 2.2-1

Applying KCL at node-A, we get –5 – (–2) – *i*_{1} ⇒ 0 ⇒ *i*_{1} = –3 A Applying KCL at node-B, we get (–2) + (–2) – *i*_{2} = 0 ⇒ *i*_{2} = –4 A

Applying KCL at node-C, we get 5 – (–2) + *i*_{3} = 0 ⇒ *i*_{3} = –7 A

Applying KVL in the loop * I*_{1}*–V*_{1}*–V*_{3}, we get * v*_{1} –10–5 = 0 ⇒ *v*_{1} = 15 V

Applying KVL in the loop *I*_{3}–*V*_{1}–*V*_{2}, we get *v*_{3} –10 + (–10) = 0 ⇒ *v*_{3} = 20 V

Applying KVL in the loop *I*_{2}–*V*_{2}–*V*_{3}, we get –*v*_{2} – (–10) –5 = 0 ⇒ *v*_{2} = 5 V

**Fig. 2.2-4 **Circuit with nodes and reference directions identified

Power * delivered by an element* is given by * -vi,* where * v * and * i* are its voltage and current variables, respectively, as per passive sign convention.

** Example: 2.2-2**

Express* i*_{2}(*t*), *i*_{4}(*t*) and *i*_{5}(*t*) in terms of *i*_{1}(*t*), *i*_{3}(*t*) and *i*_{6}(*t*) in the circuit shown in Fig. 2.2-5.

**Fig.2.2-5** Circuit for Example 2.2-2

**Solution**

Applying KCL at node-1, we get * –i*_{1}(*t*) + * i*_{4}(*t*) + * i*_{6}(*t*) = 0 ⇒ * i*_{4}(*t*) = *i*_{1}(*t*) – * i*_{6}(*t*)

Applying KCL at node-3, we get –*i*_{5}(*t*) + * i*_{3}(*t*) – * i*_{6}(*t*) = 0 ⇒ * i*_{5}(*t*) = *i*_{3}(*t*)* – i*_{6}(*t*)

Applying KCL^{ }at^{ }node-2, we get –*i*_{4}(*t*) + * i*_{2}(*t*) + * i*_{5}(*t*) = 0 ⇒ * i*_{2}(*t*) = * i*_{4}(*t*) – * i*_{5}(*t*) = * i*_{1}(*t*) – *i*_{3}(*t*)

** Example: 2.2-3**

Fig. 2.2-6 shows the connecting wires in a part of a circuit. Some of the currents are specified for * t * ≥ 0 in Fig. 2.2-6. The current *i*_{2} is seen to be a constant in time. The current *i*_{3} is seen to approach zero as *t* → ∞. Find *i*_{1}, i_{2 } and *i*_{3} for * t * ≥ 0.

**Fig. 2.2-6** Part of a circuit referred to in Example: 2.2-3

**Solution**

Applying KVL at first node, we get 3 + * i*_{1}* –* 5(1 – *e*^{–t }) = 0 ⇒ * i*_{1}* = *2 – 5*e ^{–t} * A

*i*

_{2}is stated to be a constant in time. Let

*i*

_{2}=

*A*.

*i*

_{3 }is stated to approach zero as

*t*→ ∞. This implies that there is no DC component in

*i*

_{3}. It may contain both

*e*

^{–t }and

*e*

^{–3t}components. Let

*i*

_{3}

*= Ce*

^{–t}+ De^{–}^{3}

*Then, applying KCL at the second node, we get*

^{t}A

KCL is true at all *t*. Hence, the last equation must be valid for all * t * ≥ 0. No time-varying function can be equal to a constant unless that function itself is a constant. Thus, (*A* + 1) term in the last equation cannot be equalled by * e*^{–t} and *e*^{–3t} terms for all * t * ≥ 0. Therefore, (*A* + 1) has to be zero.

*A*= –1 ⇒

*i*

_{2}= –1 A.

A term involving * e*^{–t} cannot get cancelled by another term that involves * e*^{–3t }for all * t* ≥ 0. Therefore, coefficient of * e*^{–t} must be zero and coefficient of * e*^{–3t } also must be zero. Therefore, (5 – * C*)* =* 0 and (3 + * D*)* =* 0

**Fig. 2.2-7 **Solution for Example 2.2-3

*C*= 5 and

*D*= –3 ⇒

*i*

_{3}= (5

*e*

^{–t}–3

*e*

^{–3t}) A.

The solution is marked in Fig. 2.2-7.

##### 2.3 INTERCONNECTIONS OF IDEAL SOURCES

Interconnecting two or more ideal voltage sources in a loop may lead to a degenerate circuit. Similarly, interconnecting two or more ideal current sources in series may lead to a degenerate circuit.

Consider the interconnection of two ideal independent voltage sources as shown in Fig. 2.3-1. KVL requires that *–v _{s}*

_{1}(

*t*) +

*v*

_{s}_{2}(

*t*) = 0. Therefore,

*v*

_{s}_{1}(

*t*) has to be equal to

*v*

_{s}_{1}(

*t*) at all time instants. If they are not equal to each other, then either KVL has to yield or the ideal sources have to yield. KVL cannot

^{ }yield since it is only a disguised form of law of conservation of energy. Therefore, KVL has to be obeyed by a circuit at all instants.

**Fig. 2.3-1** Two ideal independent voltage sources in parallel

There are two ways out of this impasse for a case where * v _{s}*

_{1}(

*t*) ≠

*v*

_{s}_{2}(

*t*). The first is to declare that

*two ideal independent voltage sources cannot be connected in parallel unless their terminal voltages are equal to each other at all instants of time.*That is, we call such connections

*illegal*if

*v*

_{s}_{1}(

*t*) ≠

*v*

_{s}_{2}(

*t*). But, that is a kind of escaping the issue!

The correct way to resolve the issue is to recognise that * ideal independent voltage source* is a model for a practical electrical device, and, as in the case of any model, this model too has its range of applicability. Connecting a practical voltage source in parallel with another practical voltage source is a context in which they cannot be modelled by * ideal independent voltage source model * satisfactorily. In fact, the model is not satisfactory even when * v _{s}*

_{1}(

*t*) =

*v*

_{s}_{2}(

*t*). This is because there is no way to find out the current that will flow in the circuit. Any current can flow at any instant in such a circuit.

Thus, the only correct way to model a circuit that involves parallel connections of voltage sources (more generally, loops comprising only voltage sources) is to take into account the parasitic elements that are invariably associated with any practical voltage source. A somewhat detailed model for the two-source system is shown in Fig. 2.3-2.

*L _{i}*

_{1}and

*L*

_{i}_{2}represent the internal inductance of the sources,

*C*

_{i}_{1}and

*C*

_{i}_{2}represent the terminal capacitance of the sources and

*R*

_{i}_{1 }and

*R*

_{i}_{2}represent the internal resistance of the sources.

*L*

_{c }and

*R*

_{c }represent the inductance and resistance of connecting wires. Obviously, two practical voltage sources can be connected in parallel even if their open-circuit electromotive forces are not equal at all

*t*; only that they cannot be modelled by

*ideal independent voltage source model.*

**Fig. 2.3-2 **A detailed model for a circuit with two voltage sources in parallel

Two ideal independent current sources in series raise a similar issue (see Fig. 2.3-3). KCL requires that * i _{s}*

_{1}(

*t*)

*= i*

_{s}_{2}(

*t*) for all

*t.*Even if this condition is satisfied, there is no way to obtain the voltages appearing across the current sources. Therefore, the correct model to be employed for practical current sources that appear in series in a circuit is a detailed model that takes into account the parasitic elements associated with any practical device. More generally, if there is a node in a circuit where only current sources are connected, then those current sources cannot be modelled by

*ideal independent current source model.*

**Fig. 2.3-3 **Two ideal independent current sources in series with another element

Similar situations may arise in modelling practical dependent sources by * ideal dependent source* models. In all such cases we have to make the model more detailed in order to resolve the conflict that arises between Kirchhoff’s laws and * ideal* nature of the model.

##### 2.4 ANALYSIS OF A SINGLE-LOOP CIRCUIT

Circuit analysis problem involves finding the voltage and current variables of every element as functions of time, given the source functions. * Source functions* are the time-functions describing the electromotive force of independent voltage sources and source currents of independent current sources. They are also called the * excitation functions.* If the circuit contains * b* elements, there will be 2*b* variables to be solved for. Some of them will be known in the form of source functions. Others have to be solved for.

Element relation of each element gives us one equation per element. Thus there are * b* equations arising out of element relations. The remaining * b* equations are provided by the interconnection constraints. These equations are obtained by applying KCL at all nodes except one and KVL in all meshes (in the case of a planar circuit).

Theoretically speaking, that is all there to circuit analysis. However, systematic procedures for applying element relations, KVL equations and KCL equations would be highly desirable when it comes to analysis of complex circuits. Moreover, the fact that there are 2^{n} – 2 KCL equations for a *n*-node circuit and only (*n* – 1) of them are independent calls for a systematic procedure for writing KCL equations. Similarly, there will be * l* KVL equations for a circuit with *l*-loops and only (*b* – * n +* 1) of them will be independent. This, again, calls for some systematic procedure for extracting a set of (*b* – * n* + 1) * independent* KVL equations.

Such systematic procedures are indeed available in Circuit Theory. We will look at such procedures in detail in later chapters. However, we try to gain some experience in applying Kirchhoff’s laws and element relations to simple circuits in this section.

**Example: 2.4-1**

Refer to Fig. 2.4-1. * V*_{1}* =* 20 V, * V*_{2}* = *5 V, * R*_{1}* = *5 Ω and * R*_{2}* = *2.5 Ω. Find all element voltages and element currents. Also find the power * delivered to* all elements.

**Solution**

The first step in analysis is to assign reference directions for variables. Passive sign convention is employed to decide the reference direction for current after reference polarity for voltage is decided arbitrarily. Or, reference polarity for voltage can be decided in compliance with passive sign convention after deciding reference direction for current arbitrarily. One has to start from some point. Let us start at the first source terminal and move through the circuit in a clockwise direction.

**Fig. 2.4-1** Single-loop circuit in Example 2.4-1

The source function is already assigned polarity. This does not prevent us from assigning another voltage variable to the first source with any polarity that we may decide. However, there is simply no reason to do so. Therefore, in the case of a voltage source we accept the polarity of source function itself as the reference polarity for element voltage. Obviously, a new voltage variable is also not required. The source function itself is the value of the voltage variable for an ideal independent voltage source.

Now we have to assign a current variable with its reference direction entering the positive polarity from outside. This current is called *i*_{3} (see Fig. 2.4-2).

Now we reach the resistor *R*_{1}. We assign positive polarity of its voltage variable at the first terminal that we come across – that is, the left terminal of the resistor. Then, its current variable must enter from left as per passive sign convention.

**Fig. 2.4-2** Variable assignment and reference directions in the circuit in Example 2.4-1

Variable assignment and reference direction assignment for remaining elements is completed in a similar manner and the final variable assignment is shown in Fig. 2.4-2. The nodes in the circuit are also identified in the circuit and labelled.

The next step in the analysis is to apply KCL at any three nodes. Let us apply KCL at node-a, node-b and node-c. The result will be that –*i*_{3 } = *i*_{1} = *i*_{4} = *i*_{2}. Next, we apply KVL in the loop to get –*V*_{1}* + v*_{1}* + V*_{2} * + v*_{2}* +* 0.

The next step in the analysis is to make use of the element relations. We have already made use of the element relations of the voltage sources to set the voltage variables for the sources at their source function values themselves. The remaining elements are two resistors. The element relation for a resistor is given by Ohm’s law. The relations are

*v*

_{1}=

*R*

_{1}

*i*

_{1}

*v*

_{2}=

*R*

_{2}

*i*

_{2}

Now, these relations and the fact that –*i*_{3 } = *i*_{l} = *i*_{4} = *i*_{2 } are made use of in the KVL equation to simplify it as * –V*_{1}* + R*_{1}*i*_{1}* + R*_{2}*i*_{2}* + V*_{2}* =* 0. Note that we have eliminated *i*_{2} by using *i*_{1} = *i*_{2}. Solving this equation, we get

Now the voltage across each resistor can be worked out by using its element relation once again.

The currents through voltage sources can be noted as Substituting the numerical values in the example, we get

*i*

_{1}=

*i*

_{2}= –

*i*

_{3}=

*i*

_{4}= 2A

*v*

_{1}= 10 V;

*v*

_{2}= 5V

This solution is marked in Fig. 2.4-3. Note that the –2 A flowing * into* the first source can be marked as +2 A if the reference direction is reversed. The value of –2 A implies that *positive current flows out from the positive terminal of that source.*

**Fig. 2.4-3** Circuit solution in Example 2. 4-1

The * power delivered to an element* is given by * vi,* where * v* and * i* are its voltage variable and current variable, respectively, as per passive sign convention.

Note that the sum of power delivered to all elements is zero. The 20 V source delivers 40 W of power which is shared by the two resistors and the second source. Second source receives 10 W power from the first source and absorbs it.

Four elements were connected in this circuit with no two elements sharing the * same pair* of nodes. Two elements have only one common node. This kind of connection is called a * series connection of elements.* Obviously, in a * series connection* of elements, same current will flow in the same direction in all elements.

** Example: 2.4-2**

Solve the circuit in Fig. 2.4-4 completely.

**Solution**

This is a series connected, single-loop circuit. Therefore, same current should flow through all the elements and it is constrained to be equal to 2 A in counter-clockwise direction in the circuit by the independent current source that comes in series with other elements. Other elements have no role in deciding the circuit current.

**Fig. 2.4 _{-}4 **Circuit for Example 2.4-2

However, the current source will have to pay a price for deciding the circuit current in an autocratic manner. The price it has to pay is the amount of voltage that it has to support across its terminals and the amount of power it has to deliver or absorb. The current source will have no control over these quantities; they will be decided by rest of the elements in the circuit.

The circuit after variable assignment and reference direction assignment is shown in Fig. 2.4-5(a).

Obviously, we do not need to assign any current variable for any element in the circuit if we choose the reference directions for all element currents to coincide with the actual direction of current flow in the circuit. The polarity of element voltage variables is assigned as per passive sign convention.

Applying KVL in the loop, we get, –10 – (5 × 2) – *v*_{3} – (2.5 × 2) = 0

Therefore, *v*_{3} = –25 V. The circuit solution is marked in Fig. 2.4-5(b).

**Fig. 2.4-5** (a) Variable and reference direction assignment in the circuit in Example 2.4-2 (b) Circuit solution

Note that actually the upper terminal of current source is at a higher potential compared to the lower terminal. This indicates that the current source is delivering power. However, 2 A flows into the positive polarity terminal of the 10 V voltage source. Therefore, the voltage source is absorbing power from the current source. Thus, the current source must be delivering all the power that is absorbed by the two resistors and the voltage source. Let us verify this.

Total power absorbed by power absorbing elements is 50 W and that is equal to the power delivered by current source.

**Example: 2.4-3**

Solve the circuit in Fig. 2.4-6 completely.

**Solution**

This single-loop circuit contains a voltage-controlled voltage-source (VCVS) in series with other elements. The controlling variable of this VCVS is the voltage across the independent current source with positive polarity placed at source current delivery point.

A VCVS is a four-terminal element. The output terminal pair is connected in series with other elements in Fig. 2.4-6. But where is the input terminal pair?

**Fig. 2.4-6** Circuit for Example 2.4-3

Fig. 2.4-7 shows the actual connections involved in the circuit. The input terminal pair of the VCVS is connected across the terminals of the independent current source and the output terminal pair is connected between right-side terminal of the resistor and left-side terminal of current source. The source function value of VCVS is –0.5*v*_{x}, where *v*_{x } is the voltage sensed by its input terminal pair.

**Fig. 2.4-7** Circuit in Example 2.4-3 redrawn to show the VCVS terminal connections

The input terminal pair of an ideal VCVS is an open-circuit and does not affect the circuit behaviour in any manner. Therefore, it is sufficient to identify the controlling variable of a VCVS as in Fig. 2.4-6.

**Fig 2 4-8** Circuit variable and reference direction assignment in Example 2.4-3

The variable and reference direction assignment is shown in Fig. 2.4-8. Note that we have not assigned any new voltage variable across the current source. The voltage variable *v*_{x }itself is taken as its voltage variable. Therefore, the reference direction of current in current source and reference polarity for its voltage is not according to passive sign convention. This will not cause any problem in applying the element equation of current source in KVL. This is because the voltage across a current source is independent of its current. However, the fact that we are not using passive sign convention for this element has to be kept in mind when calculating the power delivered by this source. Adhering to passive sign convention is important in the case of passive elements since the element relation of a passive element depends on the relative polarities of voltage and current in the element.

Applying KVL in the loop, we get

The complete solution is marked in Fig. 2.4-9.

**Fig. 2.4-9** Circuit solution in Example 2.4-3

##### 2.5 ANALYSIS OF A SINGLE-NODE-PAIR CIRCUIT

A set of circuit elements is said to be connected in * parallel* if they have two nodes in common. Fig. 2.5-1 shows three circuit elements connected in parallel. All the three elements have one of their terminals connected at node-A and the other terminal connected at node-B. Circuit in Fig. 2.5-1(a) shows reference polarity assignment for the element voltage variables for the three elements. The terminal connected to the node-A is assigned the positive polarity in all the elements in this case. Circuit in Fig. 2.5-1(b) shows another possible polarity assignment. Here, the terminal that is connected to node-B is assigned the positive polarity of voltage variable in the case of second element.

**Fig. 2.5-1** Parallel connection of elements

This circuit has two meshes. We can apply KVL in those meshes. KVL applied to meshes in circuit in Fig. 2.5-1(a) will show that *v*_{1} = *v*_{2} = *v*_{3} in the circuit. However, KVL applied to meshes in circuit in Fig. 2.5-1(b) will show that *v*_{1} = –*v*_{2} = *v*_{3}. * Thus, the terminal voltages of elements connected in parallel will have same value at all t if same reference polarity assignment is used for all of them.* That is, parallel-connected elements have a * common terminal voltage* if reference polarity is same for all of them. Therefore, it is a standard practice in circuit analysis to assign positive polarity to terminals connected to a common node in the case of a set of parallel-connected elements.

A set of parallel-connected elements result in one node-pair. There will only be one independent KCL equation in a circuit containing just one node-pair. However, such a circuit may contain many meshes. Applying KVL in all those meshes will result in an already-noted conclusion that all the elements in parallel will have same terminal voltage.

**Example: 2.5-1**

Solve the circuit in Fig. 2.5-2 completely.

**Fig. 2.5 _{-}2 **Circuit for Example 2.5-1

**Solution**

The 10 V independent voltage source across the node-pair fixes the terminal voltage of all elements at 10V The current through 10 Ω will then be 10 V/10 Ω = 1 A and the current through 5 Ω will be 10 V/5 Ω = 2 A. These currents flow from top node to bottom node.

**Fig. 2.5-3 **Circuit solution in Example 2.5-1

Now we apply KCL at the top node.

Current flowing into the positive polarity of 10V source = 5 A + 1 A + 2 A = 0.

∴ Current flowing into the positive polarity of 10 V source = 2 A.

The circuit solution is marked in Fig. 2.5-3.

Total power delivered = Total power absorbed

**Example: 2.5-2**

Find the circuit solution for the circuit in Fig. 2.5-4.

**Fig. 2.5-4 **Circuit for Example 2.5-2

**Solution**

The variable assignment and reference polarity assignment is shown in Fig. 2.5-5.

**Fig. 2.5-5** Reference polarity assignment in the circuit in Example 2.5-2

The terminal voltage of all elements will be *v*_{x } with this polarity assignment. Now, *i*_{1} = *v*_{x}/2.5 A and *i*_{2} = *v*_{x}/5 A. Applying KCL at the top node, we get

Now, *i*_{1} = 2A and *i*_{2 } = 1 A. The circuit solution is marked in Fig. 2.5-6.

Power absorbed by 2.5 Ω resistor = 5 V × 2 A = 10 W

Power absorbed by 5 Ω resistor = 5 V × 1 A = 5 W

Power delivered by 2 A current source = 5 V × 2 A = 10 W

Power delivered by the dependent current source = 5 V × 1 A = 5 W

Total power delivered = Total power absorbed = 15 W

**Fig. 2.5 _{-}6 **Circuit solution in Example 2.5-2

##### 2.6 ANALYSIS OF MULTI-LOOP, MULTI-NODE CIRCUITS

The method of analysis of multi-loop, multi-node circuits, using element relations along with KCL and KVL equations, is illustrated through worked examples in this section.

**Example: 2.6-1**

Find the voltage across the dependent current source (*v*_{y}) in the circuit in Fig. 2.6-1.

**Solution**

This circuit has six elements, three nodes and three meshes. We need to find out only *v*_{y}. Let us try to solve the circuit in terms of *v*_{x }and *v*_{y } without using any other new variables

We note that

**Fig. 2.6-1 **Circuit for Example 2.6-1

Note that we have essentially employed KVL in order to arrive at these relations. Now, we can express all the currents at node-A and node-B in terms of *v*_{x } and *v*_{y}. The currents * going away from* node-A are (*v*_{AB}/3) A, (*v*_{AD}/8) A and (–*v*_{CA}/1) A. The sum of these three terms must be zero.

The currents * going away from* node-B are (–*v _{AB}*/3) A, (

*v*/5) A and

_{BC}*v*

_{x}. Sum of these terms must be zero.

Simplifying these two equations, we get

Solving these two equations, we get *v*_{x } = 2 V; *v*_{y } = 5 V

Therefore, the voltage across the dependent current source = 5 V.

**Example: 2.6-2 **

Find the power delivered by the voltage and current sources in the circuit shown in Fig. 2.6-2.

**Solution**

We need to find out the current through the 20 V voltage source and the voltage across the 5 A current source. Refer to Fig. 2.6-3.

**Fig. 2.6-2** Circuit for Example 2.6-2

**Fig. 2.6-3 **Circuit in Example 2.6-2 with variables assigned

KVL in the first mesh gives

KCL has to be satisfied at node-A.

*i*

_{2}=

*i*–

*i*

_{1}=

*i*– (4 – 2

*i*) = 3

*i*– 4 A.

Applying KCL at node-B, we get, * –i*_{2}* +** i*_{3} *–* 5 = 0 ⇒ *i*_{3} = * i*_{2}* + *5* =* (3*i* +1) A

Therefore, * V _{BC} =* 5 × (3

*i*+ 1) = 15

*i*+ 5 V.

Now we apply KVL on the outer loop of the circuit to get,

And, * V _{BC} =* 15

*i*+ 5 = 20 V.

Therefore, the current delivered by the voltage source is 1 A and the voltage appearing the current source is 20 V.

Therefore, the power delivered by the voltage source = 20 V × 1 A = 20 W

The power delivered by the current source = 20 V × 5 A = 100 W

**Example: 2.6-3**

Find *i*_{x } in the circuit shown in Fig. 2.6-4.

**Solution**

Voltage across 2 Ω resistance is 2*i*_{x } V with positive polarity at the top terminal. Therefore, the current through 4 Ω is 2*i _{x}*/4 = 0.5

*i*A from the top terminal to the bottom terminal.

_{x}**Fig. 2.6-4** Circuit for Example 2.6-3

Therefore, the current through 3 Ω must be 1.5*i _{x}* A from left to right by KCL applied to the node at which the three resistors are connected.

Therefore, the voltage across 13 Ω must be 2*i _{x} +* 3 × 1.5

*i*= 6.5

_{x}*i*V.

_{x} Therefore, the current through 13 Ω must be 6.5*i _{x}*/13 = 0.5

*i*A from the top terminal to the bottom terminal. Now, apply KCL at the current source node to get 1.5

_{x}*i*+ 0.5

_{x}*i*= 4.

_{x} ∴ *i*_{x} = 2A.

**Example: 2.6-4**

Find the ratio in the circuit shown in Fig. 2.6-5.

**Fig. 2.6-5 **Circuit for Example 2.6-4

**Solution**

The current that flows through 100 kΩ at output side is 100*i _{x}* from the bottom terminal to the top terminal. Therefore,

*v*

_{o }= –10

^{7 }

*i*V. Therefore, the voltage generated by the VCVS at input side is –0.002 × 10

_{x}^{7 }

*i*= –2 × 10

_{x}^{4}

*i*V with polarity as shown in Fig. 2.6-5.

_{x} Therefore, voltage across 40 kΩ resistance is = 20 × 10^{3 } *i _{x}* – 2 × 10

^{4 }

*i*= 0 V.

_{x}Therefore, current through 40 kΩ resistance is = 0 A.

Applying KVL in the first mesh, we get, voltage drop across 10kΩ = *v*_{s } V.

Therefore, current through 10 kΩ resistance = 10^{–4 } *v*_{s } A

Current through 40 kΩ is zero. Therefore, by KCL, *i _{x}* = 10

^{–4 }

*v*

_{s }A.

We know that * v _{o} =* –10

^{7 }

*i*

_{x}_{ }V.

##### 2.7 KVL AND KCL IN OPERATIONAL AMPLIFIER CIRCUITS

Linear dependent sources are used to model electronic amplifiers. For instance, the VCVS is the model of an ideal voltage-to-voltage amplifier. Ideal amplifiers are physically unrealisable. Operational Amplifiers try to approach the ideal.

*Operational Amplifier is a multi-stage high gain voltage-to-voltage amplifier with differential input and single-ended output.* It is an integrated circuit package. We use the short name ‘*Opamp*’ for Operational Amplifier in this book.

It is a * differential amplifier* and has two signal input terminals. It amplifies the difference between the voltages applied at input terminals. These two input voltages as well as the output voltage are referred to a common * ground* terminal.

*Ground in an Opamp is not a terminal or pin of the Opamp. It is a node outside the Opamp.* In Opamps working from a single DC power supply, the * ground* is commonly assigned to the negative of the DC source. In Opamps working * from a balanced dual DC power supply,* the * ground* is commonly taken as the midpoint of the dual supply. The output voltage is measured between a single output terminal from the Opamp and the * ground* terminal that is outside the Opamp package.

Various integrated circuit design techniques are employed to minimise the non-linear distortion in output signal arising out of non-linear transfer characteristics of transistors. However, even an Opamp cannot do away with voltage, current and rate limits. The non-linear distortion arising out of *clipping* due to one or more of these limits takes place in Opamp circuits when they are overdriven or overloaded. Thus, linear models are applicable to Opamps as long as they are not operating in one of the * limited modes.*

An ideal voltage amplifier is expected to have infinite input resistance, zero output resistance and infinite bandwidth, * i.e.,* it does not differentiate between two sinusoidal signals of same amplitude and different frequencies and provides same gain to both. * Bandwidth is a measure of variation of gain with frequency of an applied sinusoid.*

A practical Opamp has a very large input resistance (in ΜΩ) and small output resistance (in Ω) and it has finite bandwidth. Therefore, if the input applied to it is a mixture of sinusoids, it will offer different gains for different sinusoidal components at different frequencies. It will delay the output by a time-delay that will depend on the frequency. These two kinds of differential treatment to sinusoids of different frequencies lead to a difference in waveshape of output compared to that of the input. That is * distortion.* It is due to the gain of Opamp becoming a function of frequency and that happens because of capacitance of transistors. This distortion takes place even when the Opamp is in the * linear range* of operation. Therefore, it is called * linear distortion.*

Non-linear distortion changes the waveshape of output even when the input is a single frequency sinusoid. But linear distortion does not do that. Linear distortion changes the waveshape of output only when the input is * not* a single frequency sine wave, but is a mixture of sine waves of different frequencies. An ideal Opamp does not have any linear distortion.

The voltage gain of a practical Opamp is very large – typically hundreds of thousands. We hardly ever need that kind of gain in any practical application. Thus, we rarely find an Opamp being used as an amplifier without some other components (usually resistors) limiting the gain of the overall amplifier circuit to the required value that is likely to be in the range 1–100. But then, why make a circuit with a huge gain and kill its gain when it is used for amplification purposes? The simple answer is that the huge gain of Opamp is the currency that we pay for improvements in other performance measures of the overall amplifier circuit. We gain on other performance parameters by paying out gain.

For instance, the input resistance of overall amplifier can be increased and its output resistance decreased by sacrificing the gain. Its bandwidth can be increased and non-linear distortion can be decreased by sacrificing the Opamp gain.

The circuit technique that we use in order to bring about this trade-off between gain of Opamp and performance of overall amplifier circuit in which the Opamp is embedded is called * negative feedback. * We will take it up in a later section. But we note here that higher the Opamp gain, better the advantages that accrue from employing negative feedback around it.

An Opamp is expected to produce zero output when both its input terminals are connected to same voltage with respect to ground. However, practical Opamps do produce a small output under this condition. The corresponding gain is called the * common-mode gain.* The gain registered by the Opamp when it is driven by two equal but opposite sources at its input terminals is called the * differential gain. * The ratio of differential mode gain to common mode gain is defined as its *‘Common Mode Rejection Ratio* ’ and is usually quoted in decibels (dB). Decibel value of a quantity is obtained by calculating 20 times the logarithm of the quantity with 10 as the base of logarithm.

An Opamp is expected to produce zero output when both its input terminals are connected to ground. However, practical Opamps do produce non-zero output under this condition. Thus practical Opamps exhibit * output offset.*

We now arrive at a conceptual idealisation and define an Ideal Operational Amplifier (IOA) and list its features. Ideal Opamp, obviously, cannot be made. But it provides a benchmark for evaluating a practical Opamp.

*An Ideal Operational Amplifier is a voltage-to-voltage differential amplifier with infinite input resistance, infinite gain, infinite bandwidth and zero output resistance. An IOA has the following features:*

*Input resistance,* *R*_{in } → ∞

*Output resistance,* *R*_{o } → 0

*Voltage gain,* *A*_{v } → ∞

*Bandwidth, bw* → ∞

*Common mode rejection ratio (CMRR)* → ∞

*No voltage, current and slope limits *

*Zero offsets and zero input bias currents*

#### 2.7.1 The Practical Operational Amplifier

The most popular general purpose Opamp, the *μ*A 741, is available as a DIP (Dual-in-Line) package of ¼ inch × ⅜ inch size. It has 8 pins. The pin details and circuit symbol of Opamp are shown in Fig. 2.7-1. It is a dual supply Opamp and the midpoint of the supply connection is taken as ground usually.

**Fig. 2.7-1** (a) Top view of μΑ 741 IC (b) Circuit symbol and voltage polarities for an Opamp

This Opamp has a differential gain of 250,000 and CMRR of 80 dB. This implies that its common mode gain is indeed negligible. Its input resistance is about 2 ΜΩ and output resistance is about 75 Ω.

With a supply voltage of ± 12 V, its output saturation limits are 10.6 V and –11 V. It has a bandwidth of ≈ 4 Hz (very small) and a slew rate of 0.5 V/*μ*s. Its output current is limited at ±20 mA with a supply voltage of ±12 V.

Its input bias currents, called *I*_{B+ } and *I*_{B–}, are ≈ 100 nA and the difference (*I _{B}*

_{+}–

*I*

_{B}_{–}) between them can be ± 20 nA. This difference is called

*input bias offset current.*

The output of this Opamp will be at one of the saturation limits when both inputs are grounded. The offset is so high. Hence the offset voltage for Opamps is specified at input indirectly rather than at output directly. Applying a differential voltage across the inverting and non-inverting inputs of the Opamp can null the output offset. The differential voltage that has to be applied across the two input terminals in order to bring the output to zero with respect to ground is defined as the * input offset voltage* and is denoted by *v*_{io}. The value for *μ*A741 is about 2 mV. The polarity of this voltage can be decided only by experiment on the particular piece of IC that is being used.

The circuit in Fig. 2.7-1(b) shows the power supply connections in detail. However, these connections are usually suppressed in circuit diagrams involving Opamps. It is understood implicitly that the Opamps are powered properly in circuits. This is permissible since we seldom apply KCL at power supply nodes of Opamps in analysing a circuit containing Opamps. We do not apply KCL at ground node too. But that is because of the fact that we always assign the role of reference node to the ground node in Opamp circuits when we prepare the node equations of such circuits.

#### 2.7.2 Negative Feedback in Operational Amplifier Circuits

Consider the circuit in Fig. 2.7-2(a). We ignore the offsets in output in our analysis in this section. Therefore, the output in the circuit in Fig. 2.7-2(a) is given by * v _{o} = A*(

*v*

_{1}

*– v*

_{2})

*,*where

*A*is the differential mode voltage gain of the Opamp. The value of

*A*for

*μ*A741 Opamp is around 250,000. Let us assume that the power supply used is ±12 V in all the three circuits. The voltage saturation levels will be taken approximately equal to the supply voltage of 12 V. Actually, it is 10.6 V and –11 V; we ignore the difference.

**Fig. 2.7-2 **(a) Opamp on open loop (b) Opamp embedded in a resistive network (c) Opamp circuit illustrating negative feedback

Hence, the first circuit will saturate when the differential input voltage *v*_{d } = *v*_{1 } – *v*_{2 } goes out of the range (–48 *μ*V, +48 *μ*V). We usually do not need this much of gain. If *v _{d}* =

*v*

_{1}–

*v*

_{2 }is in mV or V range, the output will spend most of the time in non-linear range under saturated condition. For instance, say

*v*

_{1}

*=*0.0048sin 2

*π*

*t*V and

*v*

_{2}= 0. Then the output will be an almost clean square wave of period 1 s and amplitude of 12 V. The Opamp will be in the linear range of operation only for about 6.4 ms in 1 s. It will be in saturated condition for the remaining duration. Thus, this mode of using Opamp, called the

*open-loop*mode, is not really useful for linear amplification purposes.

Consider the second circuit in Fig. 2.7-2.

Here the Opamp is embedded in a resistive network that generates interaction between the input side of Opamp with its own output side. This interaction takes place through the resistor chain* R*_{1 }and *R*_{2}. They loop back the output of Opamp to its own input. When there is such ‘looping back’ of output of an Opamp to its input side in a circuit, we state that * the circuit employs feedback.* The *sense of feedback* can be negative or positive. We decide the * sense of feedback* in the circuit by analysing the circuit after assuming that its source is reduced to zero. The resulting circuit is shown in Fig. 2.7-2(c). We expect the output to be at zero since the Opamp was assumed to be free of offset.

Now, let us analyse the process that takes place in the system when the output is momentarily disturbed by some kind of electromagnetic pickup from some neighbouring circuit. Assume that the output voltage increased from zero level. This increase is felt at the inverting input of Opamp through the *R*_{1 } – *R*_{2 } chain. The current drawn by the inverting input of Opamp loads this potential divider. However, the Opamp has very large input resistance and hence the *R*_{1 } – *R*_{2 } potential divider may be considered unloaded. Therefore, the potential that appears at inverting input is *βv _{o}* , where

*β*is the feedback factor and is equal to

*R*

_{1}/(

*R*

_{1}+

*R*

_{2}). Therefore, when the output increases, the inverting input potential with respect to ground node also increases. This leads to a reduction in the differential voltage

*v*

_{d }that appears across the Opamp input terminals. A reduction of differential input of Opamp is followed by a reduction of its output voltage itself. Thus, we see that an inadvertent increase in Opamp output goes through the feedback loop to generate a corrective action that tends to restore the output to its pre-disturbed condition. When feedback results in this kind of corrective action, we term it as

*negative feedback*or

*degenerative feedback.*

Note that if we had connected the resistor chain at non-inverting input of Opamp and the input source to the inverting input terminal, a regenerative action, instead of a corrective action, would have taken place. An increase in output would have resulted in an increase in differential input voltage and that would have resulted in further increase in Opamp output. All circuits are under constant disturbance from other circuits. Therefore, an Opamp circuit with this kind of feedback connection will find itself going to one of the saturation levels due to some initial pickup voltage at output getting encouragement from the feedback to grow further in the same direction that it started with. This kind of feedback is called * positive feedback* or * regenerative feedback.* Positive feedback usually takes the Opamp output to saturation condition as soon as it is switched on. Obviously, positive feedback Opamp circuits cannot function as linear amplifiers.

A simple interchange of the roles of inverting input terminal and non-inverting input terminal of an Opamp in circuit changes the nature of feedback in the circuit and affects the function and operation of the circuit significantly. One has to be very careful in drawing the circuit diagrams containing Opamp. The inverting and non-inverting terminals of Opamps have to be marked properly without fail.

#### 2.7.3 The Principles of ‘Virtual Short’ and ‘Zero Input Current’

We continue with the analysis of circuit in Fig. 2.7-2(b). We have ascertained that the feedback involved in this circuit is negative in sense. Hence we expect the output to be zero when the input is zero. Now, we set out to find the output in terms of input when the input is non-zero. Assume that the Opamp is ideal. Hence, its input resistance is an open-circuit, output resistance is a short-circuit and its gain is infinity. The gain is taken as * A* first and is sent to infinity at the end of circuit solution. The circuit is redrawn with the Opamp replaced by its ideal equivalent circuit as in the circuit in Fig. 2.7-3(b). We derive the equation for output as follows:

**Fig. 2.7-3** (a) A single Opamp Amplifier circuit (b) Circuit with Opamp replaced by its equivalent circuit

We observe that the differential input *v*_{d } is only times that of what it would have been had the source been applied directly to Opamp as in the circuit in Fig. 2.7-2(a). Since the Opamp gain is very large for a practical Opamp and is infinity for an ideal Opamp, we evaluate the limit of these expressions as * A* → ∞. We get,

Hence, the gain of overall amplifier goes to 1+*R*_{2}/*R*_{1}. It is decided by external components entirely. And the differential input voltage goes to zero.

Why does the differential input voltage go to zero? If the Opamp is in linear range, its differential input voltage has to be equal to its output divided by the gain. The negative feedback present in the circuit resists any change in the output. Consider the situation when a certain voltage is suddenly applied to the input. Then the differential voltage increases suddenly since the Opamp will take a little time to adjust its output. The large differential voltage causes the Opamp output to increase. Increasing Opamp output reduces the differential input voltage through the feedback mechanism. Finally, a steady state comes up in the circuit when the output is such a value that the difference between the source voltage and the fed back voltage is exactly equal to the output divided by gain. The circuit attains equilibrium under that condition. Any deviation from this equilibrium condition will be corrected by negative feedback action. Since the gain is large, it requires only a small differential voltage to remain at this equilibrium. For instance, let *v _{s}* be 0.1 V,

*A =*250,000 and

*β =*0.1. Then

*v*0.1 × 1/(1 + 25000) = 4

_{d}=*μ*V and

*v*

_{o}= 0.1 × 250000/(1 + 25000) = 999960

*μ*V = 1 V. It requires only 4

*μ*V of

*v*

_{d }to justify ≈1 V of output since the gain is 250,000. Now if the gain is increased further, the value of

*v*

_{d }goes down further and

*v*

_{o }approaches closer to 1 V. In the limit when gain goes to infinity,

*v*

_{d }goes to zero and

*v*

_{o }goes to 1 V.

But will *v*_{d } be zero if *v*_{s } is 10 V? No, since the amplifier will saturate and will be in the non-linear range of operation. The large gain that is effective in linear range of operation is not available when the Opamp is operating in voltage-limited or current-limited or slope-limited modes of operation. Hence, we may conclude that the differential voltage across the non-inverting input terminal and the inverting input terminal of an Opamp is arbitrarily close to zero if the Opamp is under negative feedback and is in its linear range of operation. Thus, the two input terminals, though are not connected together, are virtually at the same potential under these conditions and behave as if they are shorted together. Therefore, there is a * virtual short* across the input terminals of an Opamp working in its linear range of operation in a negative feedback circuit. We emphasise this principle in the following.

The input terminals of an ideal Opamp in a negative feedback circuit behave as if there is short-circuit across them.

The input terminals of a practical Opamp with large gain behave as if there is short-circuit across them provided the Opamp is in a negative feedback circuit and it is operating in its linear range.

The input resistance of an ideal Opamp is infinite and hence the Opamp does not draw any current at its input terminals. The input resistance of a practical Opamp is large and the current drawn by the input terminals is usually negligible compared to currents elsewhere in the circuit. This remains true even when the Opamp is in its non-linear range of operation. We state this principle in the following.

**The zero input current principle**

The input terminals of an ideal Opamp do not draw any current from the circuit in which the Opamp is embedded.

Thus, from the point of view of input currents drawn by the ideal Opamp, its input terminals represent an open-circuit, and, from the point of view of differential input voltage, the same two terminals represent a short-circuit. This model for an Opamp is called the * Ideal Opamp Model* (IOA Model). * It is emphasised again that IOA model will lead to correct analysis only if the Opamp is in a negative feedback circuit and is working in its linear range of operation.*

#### 2.7.4 Analysis of Operational Amplifier Circuits Using the IOA Model

The principles enunciated in the preceding section can be used to develop a much-simplified analysis procedure for circuits containing Opamps. The procedure is outlined in the following:

- Ascertain whether the circuit has negative feedback or positive feedback. If it is a positive feedback circuit, the IOA model cannot be used for its analysis. Only the principle of zero input current will be applicable to such circuits. Other analysis procedures using nodal analysis or mesh analysis along with zero input current principle will then be needed.
- Prepare KCL equations at all nodes except ground node. Ground node is taken as the reference node. Use the principle of zero input current in writing the KCL equations.
- Apply the principle of virtual short on all Opamps in the circuit to reduce the number of KCL equations and solve the reduced set of equations.

This procedure is illustrated in the case of various Opamp circuits in the remainder of this section. These circuits not only serve as illustrations for the technique of analysis but also introduce the reader to Opamp circuits that are frequently employed in analog signal processing applications. In fact, the popularity of these circuits provides motivation for inclusion of Opamp circuits in a book on basic circuit theory.

#### The Non-Inverting Amplifier Circuit

The first circuit is called * Non-Inverting Amplifier* or * Amplitude Scalar.* We have already used this circuit in the preceding sections. It is shown in the circuit in Fig. 2.7-4 (a). The circuit in Fig. 2.7-4 (b) shows the application of the principles of zero input current and virtual short.

**Fig. 2.7-4 ** (a) The non-inverting amplifier circuit (b) Application of IOA model to the amplifier circuit

We do not need any KCL equations here. The potential divider formed by *R*_{1}–*R*_{2} is unloaded at its output and is driven by an ideal dependent voltage source with zero series resistance. Therefore potential at inverting input is *β**v _{o},* where

*β*=

*R*

_{1}/(

*R*

_{1}+

*R*

_{2}). The potential at non-inverting input is

*v*. It will be

_{s}*v*even if the source has series resistance. This is due to the fact that the current in input line is zero. Now, we apply the principle of virtual short to equate these two potentials. Both potentials are referred to the ground node.

_{s}Therefore, the gain of non-inverting amplifier It has infinite input resistance and zero output resistance as per IOA model. Practically, input resistance and output resistance of Opamp will limit these.

#### The Voltage follower Circuit

This circuit is a special case of the non-inverting amplifier circuit. *R*_{2 } is kept at zero value and *R*_{1 } is made an open-circuit. The resulting gain will be unity. The unity gain amplifier is used as a buffer amplifier to interconnect circuits without interfering with each other. When a second circuit is connected as a load to the first circuit, the performance of first circuit is affected by the input characteristics of the second circuit and the performance of second circuit is affected by the output characteristics of the first circuit. A unity gain buffer amplifier interfaces the two circuits by providing an infinite load resistance to the first circuit and an ideal voltage source with zero series resistance to the second circuit. Voltage follower circuit shown Fig. 2.7-5 is used in buffering applications.

**Fig. 2.7-5** The^{ }voltage follower^{ }circuit

#### The Inverting Amplifier Circuit

This amplifier is shown in Fig. 2.7-6.

Assume that input is grounded and the output voltage deviates upwards from zero due to some temporary disturbance. Then the voltage fed back to the inverting terminal increases, thereby effecting a decrease in the differential input voltage. This leads to corrective action at the output. Hence, there is negative feedback in this circuit.

**Fig. 2.7-6** The inverting amplifier circuit

The non-inverting input is grounded. Therefore, by virtual short principle, the potential at the inverting input is also zero. That is, the inverting terminal is * virtually grounded.* Hence, the current in *R*_{1} has to be *v _{s}* /

*R*

_{1 }A. Thus, the Opamp with grounded non-inverting terminal converts the input voltage source into a current source with the conversion factor decided by

*R*

_{1}.

The input current into the inverting input terminal is zero by zero input current principle. Therefore, the current in *R*_{2} has to be *v _{s}*/

*R*

_{1 }A by KCL at inverting input. This current flow results in a voltage drop of

*v*

_{s}*R*

_{2}/

*R*

_{1}V with the polarity shown in Fig. 2.7-6. Applying KVL in a loop starting at non-inverting input terminal and ending at the ground node, we get

Therefore, The gain of the amplifier is –*R*_{2}/*R*_{1}. The output undergoes a sign change with respect to input and hence the name – * Inverting Amplifier.* The input resistance of the amplifier is *R*_{1}. The output resistance of this amplifier is zero as per IOA model and is small-valued in practice.

#### The Inverting Summer

The circuit of * Inverting Summer* is shown in Fig. 2.7-7.

**Fig. 2.7-7** The inverting summer amplifier circuit

The inverting input terminal is at virtual ground. Therefore, the currents through *R*_{1 } and *R*_{2 } are *v*_{1}/*R*_{1} and *v*_{2}/*R*_{2}, respectively. These two currents add at the inverting node and flow into the feedback resistor * R _{F},* producing a voltage drop of

*v*

_{1}(

*R*

_{F}/R_{1})

*+ v*

_{2}(

*R*

_{F}/R_{2}) across it. Therefore, the output voltage is – [

*v*

_{1}(

*R*

_{F}/

*R*

_{1}) +

*v*

_{2}(

*R*/

_{F}*R*

_{2})].

The circuit acts as an inverter summer if *R*_{1} = *R*_{2} = * R _{F} = R.* Then the output voltage will be –(

*v*

_{1}+

*v*

_{2}).

More than two sources can be connected to summer in the same manner. Essentially, the virtual ground at inverting input terminal results in a voltage to current conversion in all source lines. The inverting input acts as a * summing node* where all the input line currents get added. The sum current gets pushed into the feedback resistor since Opamp input terminal does not draw any current.

#### The Non-Inverting Summer Amplifier

The non-inverting summer amplifier with three inputs is shown in Fig. 2.7-8.

The gain from non-inverting input terminal to the output terminal will be 1+(*k*–1)*R*/*R* = *k*. We need to find the potential at non-inverting input terminal in terms of *v*_{1}, *v*_{2} and *v*_{3} in order to obtain an expression for *v*_{o } in terms of the source voltages. The node potential at non-inverting input is marked as *v*. Applying KCL at this node and using the principle of zero input current, we get the following node equation, where the *G*’s represent the conductance values.

**Fig. 2.7-8** The non-inverting summer amplifier circuit

If there are * n* inputs connected at the input, the equation for *v*_{o } gets generalised to

If all the input resistors are equal and * k* = *n*, then the circuit performs the addition function without any gain,

It may be observed that the gain for each source voltage is dependent on the conductance values of resistors in * all* source lines. Hence, addition of an extra source will affect the gain for all other sources. The inverting summer circuit does not suffer from this shortcoming, thanks to the inverting input terminal acting as a * summing node for currents.*

If one can spend two Opamps, an inverting summer followed by an inverting amplifier with a gain of –1 is a better solution than the non-inverting summer.

#### The Subtractor Circuit

The * Subtractor Circuit* is shown in Fig. 2.7-9.

The principle of zero input current is used to arrive at the conclusion that the potential dividers connected at both input terminals are unloaded. Therefore, the potential of non-inverting input terminal is *kv*_{1}/(*k*+1).

**Fig. 2.7-9** The subtractor circuit using a single Opamp

The potential at the inverting input terminal is the same as the potential at non-inverting input terminal by the principle of virtual short. Therefore, the potential at inverting terminal is *kv*_{1}/(*k*+1) V with respect to ground node.

Now, we write the KCL at inverting input terminal and make use of principle of zero input current while writing down the equation. The KCL equation is obtained as

Solving for *v _{o}*, we get,

*v*_{o } = * k* (*v*_{1} – *v*_{2}). * k* = 1, if all resistors chosen are equal.

The circuit is expected to give zero output if *v*_{1} = *v*_{2}. That is, its common mode gain is expected to be zero. However, in practice it isn’t. The reason is the invariably present deviations in the resistance value of resistors from their nominal values. Resistors have a tolerance factor. If the actual values of resistance of resistors is such that the ratio between the two resistors connected to inverting terminal is different from the ratio of resistors connected at the non-inverting terminal, the common mode gain of the circuit will not be zero. This circuit is also called * differential amplifier.* The input resistance offered to the sources depends on the value of * R* used in the circuit. The performance of this circuit in amplifying voltage difference is satisfactory for less stringent applications.

**Example: 2.7.1**

Find the value of * V* in the circuit in if the output is observed to be 0 V.

**Solution**

This is a non-inverting amplifier of gain = The output voltage will be 10 times the voltage at non-inverting pin with respect to ground. If the output is seen to be zero, then the voltage at non-inverting input must be 0 V.

**Fig. 2.7-10 **Circuit for Example 2.7.1

Input terminals of Opamp do not draw current. Hence, the 2 mA delivered by the current source will flow through 10 k resistor. Therefore, the voltage at the non-inverting pin is * V* + 10 k × 2 mA = (*V* + 2) V. * V* has to be – 2 V for this to become 0 V.

**Example: 2.7.2**

Find the output voltage in the Opamp circuit in Fig. 2.7-11.

**Solution**

Inverting pin is at the same potential as that of the non-inverting pin by virtual short principle. Therefore, inverting pin is at 2 V. Hence, the voltage drop across 1 k resistor is (*v _{S}* (

*t*) – 2) V. Therefore, the current that comes to inverting pin from 1 k resistor line is (

*v*(

_{S}*t*) – 2) mA. The current source delivers 4 mA to the same pin. Inverting pin of Operational Amplifier does not draw any current. Therefore, the current that goes into 10 k will be [4 + (

*v*(

_{S}*t*) – 2)] = (

*v*(

_{S}*t*) + 2) mA. Therefore, drop across 10 k will be (10

*v*(

_{S}*t*) + 2) V. The inverting pin is at 2 V. Therefore, the output voltage = 2 V– (10

*v*(

_{S}*t*) + 2) V = –10

*v*(

_{S}*t*) V.

**Fig. 2.7-11 **Circuit for Example 2.7.2

##### 2.8 SUMMARY

- Let a circuit contain
*b*-elements,*l*-loops and*n*-nodes, and let it have a unique solution. Then the ‘circuit analysis problem’ involves solving for 2*b*variables – one voltage variable and one current variable per two-terminal element.*b*equations are obtained by using the element relation of*b*elements. The remaining*b*equations come from applying Kirchhoff’s Current Law and Kirchhoff’s Voltage Law. KVL and KCL equations depend only on the topology of the circuit and do not depend on the nature of elements. - A
*node*in a circuit is a junction point at which the connection leads of two or more points join together. The*node*is part of the connecting wire. Hence, according to the assumptions involved in lumped parameter circuit theory, there is negligible charge storage and negligible rate of change of charge storage at a node. - Therefore, the net positive current that enters (or leaves) a node in a circuit through all the connecting wires connected at that node has to be zero. This is the Kirchhoff’s Current Law.
- Kirchhoff’s Current Law can be stated in three forms as follows:
- Kirchhoff’s Current Law (KCL) states that the algebraic sum of currents leaving a node in a lumped parameter circuit is equal to zero on an instant-to-instant basis.
- Kirchhoff’s Current Law (KCL) states that the algebraic sum of currents entering a node in a lumped parameter circuit is equal to zero on an instant-to-instant basis.
- Kirchhoff’s Current Law (KCL) states that the sum of currents entering a node in a lumped parameter circuit through some wires must be equal to the sum of currents leaving the same node through the remaining wires on an instant-to-instant basis.

- Kirchhoff’s Current Law is also valid for any closed surface that intersects connecting wires and encloses more than one node and one or more elements without intersecting any element. Such a closed surface is called a
*supernode*of the circuit. - KCL equations for any (
*n*–1) nodes in a*n*-node circuit will form an independent set of equations. - A
*loop*in a circuit is*closed path*traced through nodes, connecting wires and elements such that no node is visited more than once in one complete traversal of the closed path. - Kirchhoff’s Voltage Law for such a loop in a circuit can be stated in three equivalent forms as follows:
- Kirchhoff’s Voltage Law states that the algebraic sum of voltages in any closed path in a lumped parameter circuit is zero on an instant-to-instant basis.
- Kirchhoff’s Voltage Law states that the sum of ‘voltage rises’ in any closed path in a lumped parameter circuit is zero on an instant-to-instant basis.
- Kirchhoff’s Voltage Law states that the sum of ‘voltage drops’ in any closed path in a lumped parameter circuit is zero on an instant-to-instant basis.

- A
*planar*circuit is one that can be represented on a paper without crossing of connecting wires. Those closed loops that do not contain other loops within them in a planar circuit are called its*meshes.* - The KVL equations for meshes in a planar circuit will be an independent set of equations.
- A set of two-terminal elements is said to be
*series-connected*if a common current can flow through them. - A set of two-terminal elements is said to be
*parallel-connected*if they share the same node-pair. In this case, it is possible to make the terminal voltage variables of all such elements a common variable by suitable reference polarity assignment for voltage variables. *An Operational Amplifier is a muti-stage high gain voltage-to-voltage amplifier with differential input and single-ended output.*It is a*differential amplifier*and has two signal input terminals. It amplifies the difference between the voltages applied at input terminals. These two input voltages as well as the output voltage are referred to a common*ground*terminal.- An Ideal Operational Amplifier (IOA) is a voltage-to-voltage differential amplifier with infinite input resistance, zero output resistance, infinite differential gain, zero common mode gain, infinite bandwidth, no output current and rate restrictions, no offsets and no input bias currents.
- A simple interchange of the roles of inverting input terminal and non-inverting input terminal of an Opamp in circuit changes the nature of feedback in the circuit and affects the function and operation of the circuit significantly.
*The principle of virtual short*– The input terminals of an ideal Opamp in a negative feedback circuit behave as if there is a short-circuit across them. The input terminals of a practical Opamp with large gain behave as if there is short-circuit across them provided the Opamp is in a negative feedback circuit and it is operating in its linear range.*The principle of zero input current*– The input terminals of an ideal Opamp do not draw any current from the circuit in which the Opamp is embedded.- These two principles can be used to analyse Opamp circuits quickly, provided the Opamp is in a negative feedback circuit and is in its linear range of operation.

##### 2.9 PROBLEMS

- Some voltage and current variables are specified at an instant in the circuit in Fig. 2.9-1. Find the remaining variables at that instant as per the reference directions marked.
**Fig. 2.9-1** - The circuit shown in Fig. 2.9-2 is a DC circuit containing only resistors and independent sources. Some voltage and current variables are specified in the circuit. (i) Find the remaining variables with reference directions as shown. (ii) Identify those elements that
*have to be*sources. (iii) Identify those elements that*can be*resistors. (iv) Identify the elements that receive positive power and calculate the total power absorbed by them. (v) Identify the elements that deliver positive power and calculate the total power absorbed by them.**Fig. 2.9-2** - (i) Express all element currents in terms of
*i*_{3},*i*_{4},*i*_{7}and*i*_{8}in the circuit in Fig. 2.9-3. (ii) Express all element voltage variables in terms of*v*_{3},*v*_{4},*v*_{7}and*v*_{8}.**Fig. 2.9-3** - The circuit shown in Fig. 2.9-4 is known to contain only resistors and independent sources. (i) Find all the voltage and current values in the circuit. (ii) What is the minimum number of independent sources that the circuit must contain? (iii) Draw the circuit configuration that contains minimum number of independent sources assuming that all sources are voltage sources. (iv) Draw the circuit configuration that contains minimum number of independent sources assuming that all sources are current sources.
**Fig. 2.9-4** - (i) Show that the circuit solution for the circuit shown in Fig. 2.9-5 is the same as the solution for the circuit in Fig. 2.9-4. (ii) Calculate the power
*delivered by*all current sources and voltage sources in the circuit and verify that the total power absorbed in the circuit is equal to the total power delivered in the circuit.**Fig. 2.9-5** - (i) Complete the DC circuit solution for the circuit in Fig. 2.9-6. (ii) Construct
*three*different circuits that have same circuit solution as in the circuit in Fig. 2.9-6 using three independent current sources and three independent voltage sources in all cases. Specify the source function values in each case.**Fig. 2.9-6** - Two identical DC practical voltage sources with internal electromotive force of
*E*V and internal resistance of*R*ohms each are paralleled to meet a steady load current demand of*I*A represented by an independent current source in the circuit shown in Fig. 2.9-7. (i) Derive expressions for the currents delivered by the sources (*I*_{1}and*I*_{2}) and the terminal voltage*V*_{t }in terms of*E*,*I*and*R*. (ii) What is the ratio of*I*_{1 }to*I*_{2 }for an arbitrary value of*R*? (iii) What is the value of this ratio when*R*→ 0 in an identical manner in both sources? (iv) What is the difference between*I*_{1}and*I*_{2}if*R*= 0 in both sources? (v) What is the ratio of*I*_{1}to*I*_{2 }if*R*= 0? Can it be determined uniquely. [Hint: There is a difference between ‘a quantity that tends to approach zero value’ and ‘a quantity that has a zero value’.]**Fig. 2.9-7** - Two identical DC practical current sources with a source current value of
*I*A and internal resistance of*R*ohms each are connected in series to meet a steady load voltage demand of*V*V represented by an independent voltage source in the circuit shown in Fig. 2.9-8. (i) Derive expressions for the voltages appearing across the sources (*V*_{1}and*V*_{2}) and the terminal current*I*_{t }in terms of*I*,*V*and*R.*(ii) Show that the two current sources share the load voltage equally for any finite value of*R*provided the resistance value remains equal for both sources. (iii) Show that the manner in which two current sources share the load voltage cannot be determined if the two current sources are*ideal.***Fig. 2.9-8** - Find the range of
*R*such that the voltage*V*_{o }remains between 9 V and 9.5 V in the circuit in Fig. 2.9-9.**Fig. 2.9-9** - Find the range of
*R*such that the current*I*_{o }remains between 0.3 A and 0.35 A in the circuit in Fig. 2.9-10.**Fig. 2.9-10** - Find the value of all resistors in the circuit in Fig. 2.9-11 and calculate the total power dissipated in them.
**Fig. 2.9-11** - Refer to Fig. 2.9-12. The voltage across 0.01 F capacitor is 30 V at
*t =*0. The voltage across 0.02 F capacitor is 60 V at*t*= 0. (i) Find the value of*v*at_{x}*t*= 0. (ii) Find the rate of change of capacitor voltage variables with respect to time at*t*= 0.**Fig. 2.9-12** - Refer to Fig. 2.9-13. The currents flowing in the inductors at
*t =*0 are as marked in Fig. 2.9-13. (i) Find the value of*i*at_{x}*t =*0. (ii) Find the time-rate of change of currents in the inductors at*t =*0.**Fig. 2.9-13** - Find the currents in all the resistors in the circuit shown in Fig. 2.9-14 by applying Kirchhoff’s laws with
*I*_{1}= 2 A,*I*_{2}= 5 A and*I*_{3}= 2 A. [Hint: Write KCL equations at three nodes A, B and C in terms of voltage variables*V*,_{AD}*V*and_{BD}*V*_{CD}_{ }and resistance values.]**Fig. 2.9-14** - Solve the circuit shown in Fig. 2.9-15 and find the power consumed by the resistors, power delivered by the independent source and power delivered by the dependent source.
**Fig. 2.9-15** - Solve the circuit shown in Fig. 2.9-16 completely and find out
*V*Also find the total power dissipated in the circuit and the power delivered by independent and dependent sources._{AB}.**Fig. 2.9-16** - Find the circuit current and power delivered by all the six elements in the circuit shown in Fig. 2.9-17.
**Fig. 2.9-17** - Find the voltage across the parallel combination in the circuit shown in Fig. 2.9-18. Also find the power absorbed by all the elements in the circuit.
**Fig. 2.9-18** - Find the energy delivered to the 9 Ω resistor and dissipated in the 2 Ω resistors in the circuit shown in Fig. 2.9-19 during [0, 2 s] if
*v*_{s}_{1}= 10 sin100*πt*V and*v*_{s}_{2}= 10 V.**Fig. 2.9-19** - Find the charge delivered to the 6 V voltage source from
*t*= 0 to*t*= 2 s in the circuit in Fig. 2.9-20.*i*_{s}_{1}= 2+*e*^{–t}A for*t*≥ 0 and 0 A for*t*< 0.*i*_{s}_{2}=*te*^{–2t }A for*t*≥ 0 and 0 A for*t*< 0.**Fig. 2.9-20** - Find the coefficients
*k*_{1 }and*k*_{2}for the dependent sources in the circuit in Fig. 2.9-21.**Fig. 2.9-21** - Find
*α*and*β*in the circuit in Fig. 2.9-22.**Fig. 2.9-22** - Design an Opamp circuit to produce
*v*(_{o}*t*) = 3 + 7 sin 200*πt*V using ±12 V power supply and a signal source*v*(_{S}*t*) = 0.5 sin 200*πt*V. - Find
*i*,_{L}*i*,_{s}*i*and_{o}*v*in the voltage to current converter in Fig. 2.9-23 designed to produce a constant current in a 10 Ω load._{o}**Fig. 2.9-23** - (i) Show that the current in the load resistance
*R*_{L }in the circuit in Fig. 2.9.24 is independent of*R*_{L }if (*R*_{3}+*R*_{4}) >>*R*_{5}//*R*. (ii) Find_{L}*i*,_{L}*i*,_{s}*i*and_{o}*v*with the component values shown._{o}**Fig. 2.9.24** - Show that
*v*(_{o}*t*)*=*(1 +*R*_{2}/*R*_{1})(*v*_{1}–*v*_{2}) in the circuit in Fig. 2.9-25.**Fig. 2.9-25** - (i) Show that the overall feedback is of degenerative nature in the circuit in Fig. 2.9-26. (ii) Derive expressions for gains at the outputs of both Opamps. (iii) Evaluate the gain
*v*/_{o}*v*with_{s}*R*_{4 }= 99*R,**R*_{3}= 100*R*and*R*_{2}= 9*R*_{1}. (iv) Design the circuit using*μ*A741 IC with the above constraints on resistances.**Fig. 2.9-26**